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US20060205206 Method of eliminating photoresist poisoning in damascene applications  
A method is provided for processing a substrate including treating a surface of a dielectric layer comprising silicon and carbon by exposing the dielectric layer comprising silicon and carbon to a...
US20070077761 TECHNIQUE FOR FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAPPING LAYER  
By providing a conductive capping layer for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing...
US20050266682 Methods and apparatus for forming barrier layers in high aspect ratio vias  
In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD)...
US20090273022 CONDUCTIVE HARD MASK TO PROTECT PATTERNED FEATURES DURING TRENCH ETCH  
A monolithic three dimensional memory array is formed by a method that includes forming a first memory level above a substrate by i) forming a plurality of first substantially parallel conductors...
US20050170643 Forming method of contact hole, and manufacturing method of semiconductor device, liquid crystal display device and EL display device  
When forming a contact hole by a conventional manufacturing step of a semiconductor device, a resist is required to be formed on almost entire surface of a substrate so as to be applied on a film...
US20130330922 Semiconductor Constructions and Assemblies and Electronic Systems  
The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated...
US20100252930 Method for Improving Performance of Etch Stop Layer  
A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes...
US20070267725 Semiconductor chip, method of manufacturing the semiconductor chip and semiconductor chip package  
In a semiconductor chip, a body has a top surface where a pattern is formed, an underside surface opposing the top surface and a plurality of side surfaces. A plurality of electrode pads are...
US20060270216 Phase change memory cell defined by a pattern shrink material process  
One embodiment of the present invention provides a memory cell device. The memory cell device includes a first electrode, a phase-change material adjacent the first electrode, and a second...
US20050026424 Fabrication method of semiconductor integrated circuit device  
The following defects are suppressed: when an interlayer insulating film including a silicon carbide film and an organic insulating film is dry-etched to form interconnection grooves over...
US20050287749 Methods for forming openings in doped silicon dioxide  
Methods of forming openings in doped silicon dioxide layers and of forming self aligned contact holes are provided. The openings are generally etched in a plasma processing chamber. An etchant gas...
US20080124917 Method of manufacturing a semiconductor device having air gaps  
In a method of manufacturing a semiconductor device having air gaps, an organic sacrificial layer pattern is formed on a semiconductor substrate, wherein the organic sacrificial layer pattern...
US20100190334 THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor circuit structure includes a support substrate which carries an interconnect region and electronic circuitry. The semiconductor circuit structure includes a device substrate...
US20150111374 SURFACE TREATMENT IN A DEP-ETCH-DEP PROCESS  
Embodiments of present invention provide a method of forming semiconductor devices. The method includes creating an opening in a semiconductor structure; depositing a first layer of metal inside...
US20100013049 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME  
A first multilayer body is formed by alternately layering dielectric films and electrode films on a substrate. Then, an end portion of the first multilayer body is processed into a staircase...
US20050277289 Line edge roughness reduction for trench etch  
A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the...
US20050042860 Method for eliminating reaction between photoresist and OSG  
A method of forming a microelectronic device while preventing photoresist poisoning. Various layers of conductive metals and dielectric materials are deposited onto a substrate in selective...
US20130093092 ELECTRONIC DEVICE AND METHOD FOR PRODUCING SAME  
An electronic device includes: a first insulating film; an interconnection trench on a surface of the first insulating film; an interconnection pattern composed of Cu, the interconnection trench...
US20120256324 Method for Improving Performance of Etch Stop Layer  
A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes...
US20080203576 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting...
US20060264027 Air gap interconnect structure and method thereof  
Methods for fabricating interconnect structures implementing air gaps therein is provided. In one embodiment, a semiconductor substrate with a first barrier layer formed thereon is provided. A...
US20120153483 BARRIERLESS SINGLE-PHASE INTERCONNECT  
A method of forming an interconnect structure and an integrated circuit including the interconnect structure. The method includes: depositing a dielectric layer over a conductive layer; forming an...
US20130009305 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor device having a first via and a first interconnect supplying a high current is provided in which a first surface having the first via and the first interconnect is planar. The...
US20090075474 METHODS FOR FORMING DUAL DAMASCENE WIRING USING POROGEN CONTAINING SACRIFICIAL VIA FILLER MATERIAL  
Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer...
US20050233580 Alignment pattern for a semiconductor device manufacturing process  
An alignment pattern comprises at least a sloped surface which communicates between a top surface of an inter-layer insulator extending over a surface of a substrate and a field oxide film...
US20050151263 Wiring structure forming method and semiconductor device  
After a via hole to connect a lower wiring and an upper wiring not shown is formed in an insulating film using an etching stopper film and a hard mask, a base film made from tantalum is formed on...
US20090200683 INTERCONNECT STRUCTURES WITH PARTIALLY SELF ALIGNED VIAS AND METHODS TO PRODUCE SAME  
An interconnect structure having partially self aligned vias with an interlayer dielectric layer on a substrate, containing at least two conducting metal lines that traverse parallel to the...
US20070202689 Methods of forming copper vias with argon sputtering etching in dual damascene processes  
A method of forming a via using a dual damascene process can be provided by forming a via in an insulating layer above a lower level copper interconnect and etching into a surface of the lower...
US20060279000 Pre-solder structure on semiconductor package substrate and method for fabricating the same  
A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer...
US20060246717 METHOD FOR FABRICATING A DUAL DAMASCENE AND POLYMER REMOVAL  
A method for fabricating a dual damascene includes a partial etching process, a photoresist layer stripping process, and a blanket etching process. After the blanket etching process, an in-situ...
US20060099802 Diffusion barrier for damascene structures  
A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed....
US20060009026 Method of fabricating wiring board  
In a wiring board fabrication method including a wiring formation process using a damascene method, via holes reaching an underlying wiring layer are formed in an interlayer insulating layer...
US20050032357 Dielectric materials and methods for integrated circuit applications  
An integrated circuit device is provided having a substrate and areas of electrically insulating and electrically conductive material, where the electrically insulating material is a hybrid...
US20110254165 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PRODUCTION METHOD THEREOF  
In processes after a TSV is formed, occasionally, cracks appear in an insulation film after the insulation film that is a film for preventing Cu from diffusing is formed and the exposed Cu...
US20090212397 Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit  
A method of manufacturing an ultra thin integrated circuit comprises providing a substrate having a front side, a back side, and an edge extending from the front side to the back side; creating a...
US20070148963 Semiconductor devices incorporating carbon nanotubes and composites thereof  
Methods of utilizing carbon nanotubes or composites thereof as hole plugs in vias or in contact holes for connecting conductive layers in integrated circuits are disclosed. Integrated circuits and...
US20050095848 Method of fabricating a stacked local interconnect structure  
A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and...
US20080136037 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A method for manufacturing a semiconductor device, the method including: the first step of forming an insulating film over a substrate of which surface side has a first conductive layer, and...
US20130171817 STRUCTURE AND METHOD FOR REDUCING VERTICAL CRACK PROPAGATION  
A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal...
US20110021020 SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREOF  
A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation...
US20100237504 Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices  
A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is...
US20070093055 HIGH-ASPECT RATIO CONTACT HOLE AND METHOD OF MAKING THE SAME  
A substrate has thereon a conductive region to be partially exposed by the contact hole, a contact etch stop layer overlying the substrate and covering the conductive region, and an inter-layer...
US20050186774 Method of using micro-contact imprinted features for formation of electrical interconnects for substrates  
An imprinting stamp to imprint an opening in a material layer in which the imprint stamp has a coating of a seed material. The seed material is transferred onto the surface within the opening to...
US20090017613 METHOD OF MANUFACTURING INTERCONNECT SUBSTRATE AND SEMICONDUCTOR DEVICE  
An interconnect substrate includes an interconnect, an insulating layer, a non-photosensitive resin layer, a photosensitive resin layer, a first electrode pad, and a second electrode pad. The...
US20060024958 HSQ/SOG dry strip process  
A spin-on dielectric (120) strip process. Instead of a wet strip, a dry strip process is used to remove the spin-on dielectric (120). In a via-first dual damascene method, a via (116) may be...
US20120241834 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element...
US20080113505 METHOD OF FORMING A THROUGH-SUBSTRATE VIA  
A method for achieving a through-substrate via through a substrate having active circuitry on a first major surface begins by forming a hole into the substrate through the first major surface. The...
US20140029181 INTERLAYER INTERCONNECTS AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS  
Embodiments of the present disclosure are directed towards interlayer interconnects and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor...
US20150364430 Semiconductor Device and Method of Forming a Dampening Structure to Improve Board Level Reliability  
A semiconductor device has a semiconductor die. An encapsulant is deposited over the semiconductor die. A first insulating layer is formed over the semiconductor die and encapsulant. A plurality...
US20100159693 Method of Forming Via Recess in Underlying Conductive Line  
A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the...

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