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US20140248768 Mask Assignment Optimization  
A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical...
US20140024211 USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES  
A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the...
US20150186560 SYSTEM FOR AND METHOD OF COMBINING CMOS INVERTERS OF MULTIPLE DRIVE STRENGTHS TO CREATE TUNE-ABLE CLOCK INVERTERS OF VARIABLE DRIVE STRENGTHS IN HYBRID TREE-MESH CLOCK DISTRIBUTION NETWORKS  
An electronic device fabrication tool uses only standard-size cells from a cell library to fabricate a clock distribution network on a semiconductor device, thereby reducing the cost of the...
US20150228593 Under Bump Metallization  
A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a...
US20140141607 CONTINUOUS VIA FOR POWER GRID  
A power grid of a Very Large Scale Integration (VLSI) circuit includes a sandwich structure in a cell. The sandwich structure includes a first metal layer configured to carry current along a...
US20140138842 CONTINUOUS VIA FOR POWER GRID  
A power grid of a Very Large Scale Integration (VLSI) circuit includes a sandwich structure in a cell. The sandwich structure includes a first metal layer configured to carry current along a...
US20110171825 Method of Fabricating Integrated Circuitry  
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then,...
US20120264289 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE  
An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a...
US20110254168 INTEGRATED CIRCUIT INTERCONNECT STRUCTURE  
An integrated circuit (IC) interconnect structure that includes a first via positioned in a dielectric and coupled to a high current device at one end, and a buffer metal segment positioned in a...
US20090311835 NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN  
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire...
US20140021611 Novel Copper Etch Scheme for Copper Interconnect Structure  
The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a...
US20130020712 IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFORMANCE WIRE STRUCTURE  
A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring...
US20150091172 PORE SEALING TECHNIQUES FOR POROUS LOW-K DIELECTRIC INTERCONNECT  
The present disclosure relates to a method of forming pore sealing layer for porous low-k dielectric interconnects. The method is performed by removing hard mask layer before pore sealing and/or...
US20110074041 Circuit Board with Oval Micro Via  
Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit...
US20120302057 SELF ALIGNING VIA PATTERNING  
A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the...
US20130264717 MULTI-LEVEL STACK HAVING MULTI-LEVEL CONTACT AND METHOD  
A method for forming a multi-level stack having a multi-level contact is provided. The method includes forming a multi-level stack comprising a specified number, n, of conductive layers and at...
US20130009315 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY  
A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and...
US20150249048 STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN METAL TRACE OF INTEGRATED CIRCUIT DEVICE  
An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal...
US20140264923 INTERCONNECT STRUCTURE WITH KINKED PROFILE  
Among other things, one or more interconnect structures and techniques for forming such interconnect structures within integrated circuits are provided. An interconnect structure comprises one or...
US20070049011 Method of forming isolated features using pitch multiplication  
Crisscrossing spacers formed by pitch multiplication are used as a mask to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first...
US20130169307 CONTACT RESISTANCE TEST STRUCTURE AND METHOD SUITABLE FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS  
A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test...
US20120040525 METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT  
A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level including conductive tracks and vias separated by a porous...
US20090289368 INTERCONNECT STRUCTURE HAVING ENHANCED ELECTROMIGRATION RELIABILTY AND A METHOD OF FABRICATING SAME  
An interconnect structure having improved electromigration (EM) reliability is provided. The inventive interconnect structure avoids a circuit dead opening that is caused by EM failure by...
US20120193781 CUSTOMIZED RF MEMS CAPACITOR ARRAY USING REDISTRIBUTION LAYER  
Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a...
US20060175703 Thermally responsive pressure relief plug and method of making the same  
A preformed pressure relief plug for insertion into a cavity of a vessel or valve. The plug may be formed of a eutectic alloy of bismuth, indium and tin.
US20140264881 METHODS AND STRUCTURES TO FACILITATE THROUGH-SILICON VIAS  
In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality...
US20060040491 Slot designs in wide metal lines  
A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The...
US20140264934 INTERLAYER CONDUCTOR STRUCTURE AND METHOD  
To form an interconnect conductor structure, a stack of pads, coupled to respective active layers of a circuit, is formed. Rows of interlayer conductors are formed to extend in an X direction in...
US20140199832 TITANIUM OXYNITRIDE HARD MASK FOR LITHOGRAPHIC PATTERNING  
A vertical stack including a dielectric hard mask layer and a titanium nitride layer is formed over an interconnect-level dielectric material layer such as an organosilicate glass layer. The...
US20060024958 HSQ/SOG dry strip process  
A spin-on dielectric (120) strip process. Instead of a wet strip, a dry strip process is used to remove the spin-on dielectric (120). In a via-first dual damascene method, a via (116) may be...
US20110042795 Three-Dimensional Silicon Interposer for Low Voltage Low Power Systems  
Scalable silicon (Si) interposer configurations that support low voltage, low power operations are provided. In one aspect, a Si interposer is provided which includes a plurality of...
US20130168869 Metal Layout of an Integrated Power Transistor and the Method Thereof  
The present disclosure discloses a metal layout of an integrated power transistor. The metal layout comprises a 1st metal layer, a 2nd metal layer, and a 3rd metal layer. The metal layout couples...
US20140094029 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS  
A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first...
US20140038319 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS  
A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first...
US20140203417 MITIGATION OF FAR-END CROSSTALK INDUCED BY ROUTING AND OUT-OF-PLANE INTERCONNECTS  
In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously...
US20130176073 BACK-END ELECTRICALLY PROGRAMMABLE FUSE  
A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to...
US20090121357 DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE  
A design structure for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The...
US20070202689 Methods of forming copper vias with argon sputtering etching in dual damascene processes  
A method of forming a via using a dual damascene process can be provided by forming a via in an insulating layer above a lower level copper interconnect and etching into a surface of the lower...
US20150170998 USE OF DIELECTRIC SLOTS FOR REDUCING VIA RESISTANCE IN DUAL DAMASCENE PROCESS  
An integrated circuit may include dual damascene interconnects formed using a via-first dual damascene process or a trench-first dual damascene process. The via-first process may be a...
US20130307158 CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT  
A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect...
US20130207273 Metal Line and Via Formation Using Hard Masks  
A device includes a dielectric layer, a metal line in the dielectric layer, and a via underlying and connected to the metal line. Two dummy metal patterns are adjacent to the metal line, and are...
US20130069168 SRAM LAYOUT FOR DOUBLE PATTERNING  
An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit...
US20150001734 CONDUCTIVE LINE PATTERNING  
A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two...
US20070148963 Semiconductor devices incorporating carbon nanotubes and composites thereof  
Methods of utilizing carbon nanotubes or composites thereof as hole plugs in vias or in contact holes for connecting conductive layers in integrated circuits are disclosed. Integrated circuits and...
US20100323477 INTERCONNECTIONS OF AN INTEGRATED ELECTRONIC CIRCUIT  
A method to fabricate an integrated electronic circuit includes superimposing insulating layers and metal elements distributed within said insulating layers. Each insulating layer comprises a...
US20130178057 Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique  
Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes...
US20130256910 3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS  
A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type...
US20060105567 Method for forming a dual-damascene structure  
A dual-damascene structure is formed in a porous dielectric material using an anti-reflective coating. In accordance with one embodiment, during patterning and etching if the trench portions of...
US20120208320 On-Chip RF Shields with Front Side Redistribution Lines  
A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on...
US20050239286 TWO-STEP STRIPPING METHOD FOR REMOVING VIA PHOTORESIST DURING THE FABRICATION OF PARTIAL-VIA DUAL DAMASCENE FEATURES  
A two-step stripping method for removing via photoresist during the fabrication of trench-first partial-via dual damascene features is disclosed. In the first cleaning step, inert gas (He, Ar,...