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US20130330921 Plating Process and Structure  
A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another...
US20150235960 WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an interlayer insulating film via a...
US20150145135 Electrically Conductive Laminate Structures  
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the...
US20050127516 Small viatops for thick copper connectors  
The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are...
US20060024958 HSQ/SOG dry strip process  
A spin-on dielectric (120) strip process. Instead of a wet strip, a dry strip process is used to remove the spin-on dielectric (120). In a via-first dual damascene method, a via (116) may be...
US20050189656 Micro-vias for electronic packaging  
Micro-vias may be formed, for example, using laser drilling, through a dielectric layer, down to and partially through an underlying capture pad. As a result, when the micro-via is filled with a...
US20060166490 Forming buried via hole substrates  
A preformed copper plug may be inserted into a via hole in a package substrate. The opposed surfaces of the copper preform may be covered with a solder material. Copper foils may then be applied...
US20060024953 Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess  
A method for fabricating a barrier layer. A first barrier layer (124) is deposited over a dielectric (104) including in a trench (108) and via (106). A re-sputtering process is then performed to...
US20090098728 STRUCTURE CU LINER FOR INTERCONNECTS USING A DOUBLE-BILAYER PROCESSING SCHEME  
The disclosed method forms a via between metallization layers in a semiconductor structure by patterning an insulator layer overlying a first metallization layer to include a via opening. The...
US20070111518 Method and structure for sample preparation for scanning electron microscopes in integrated circuit manufacturing  
A method for using a calibration standard. The method includes providing a calibration standard. In a specific embodiment, the calibration standard has a substrate, a thickness of material having...
US20070087554 Interconnection structure with low dielectric constant  
A method for producing an interconnection structure including at least one insulating layer having a low dielectric constant and at least one metal connection element coated with a support layer...
US20070117374 Method of forming via recess in underlying conductive line  
A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the...
US20050064676 Method of forming alignment mark  
In a first step, first trenches are formed to constitute alignment marks. In a second step, second trenches are formed, and the first and second trenches are filled with metal. When detecting...
US20100314769 FOR REDUCING ELECTROMIGRATION EFFECT IN AN INTEGRATED CIRCUIT  
An integrated circuit comprising one or more dielectric layers the or each dielectric layer being provided with one or more interconnects wherein the interconnect comprises metallic atoms moving...
US20150145593 REDISTRIBUTION STRUCTURES FOR MICROFEATURE WORKPIECES  
Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry...
US20060286797 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects  
Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain...
US20060281303 Tack & fuse chip bonding  
A method of joining contacts on two chips, each having multiple contacts, to each other involves maintaining a first of the chips at a first temperature, the first of the chips having a rigid...
US20080211112 Carbon Nanotube Bond Pad Structure and Method Therefor  
A bond pad structure (300) for an integrated circuit (IC) device uses carbon nanotubes to increase the strength and resilience of wire bonds (360). In an example embodiment there is, a bond pad...
US20080146022 Methods of Forming Conductive Interconnects  
The invention includes methods of electroless plating of nickel selectively on exposed conductive surfaces relative to exposed insulative surfaces. The electroless plating can utilize a bath which...
US20060172527 Method for forming a defined recess in a damascene structure using a CMP process and a damascene structure  
The present invention provides a technique that enables the formation of a recessed upper surface of an interconnect line to form an inlaid barrier cap layer on top of an inter-connect line to...
US20090311829 Performing Die-to-Wafer Stacking by Filling Gaps Between Dies  
An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom...
US20060267207 Method of forming electrically conductive lines in an integrated circuit  
In a method of forming a semiconductor structure, an opening is formed in a layer of a dielectric material provided over an electrically conductive feature. An etching process is performed in...
US20060134908 Polishing method  
A method for polishing an object to form wiring for a semiconductor device includes: removing part of an outside portion of a conductor layer through chemical and mechanical polishing to expose an...
US20060019485 Multi-layer wiring structure, semiconductor apparatus having multi-layer wiring structure, and methods of manufacturing them  
A multi-layer wiring structure including an upper layer wiring (second buried wiring) connected to a buried wiring (first buried wiring) in lower layer wiring grooves (first wiring grooves)...
US20080012120 Multilayer wiring substrate and manufacturing method thereof  
A multilayer wiring substrate has a plurality of wiring layers and interlayer insulating films, as well as a via of a type which connects between adjacent wiring layers and a via of a type which...
US20050164499 Electroless plating method and apparatus  
In a method of electroless plating, catalytically active nuclei are formed on a diffusion inhibiting layer (such as a barrier layer), the catalytically active nuclei being catalytically active on...
US20070099414 SEMICONDUCTOR DEVICE COMPRISING A CONTACT STRUCTURE BASED ON COPPER AND TUNGSTEN  
By providing contact plugs having a lower plug portion, formed on the basis of well-established tungsten-based technologies, and an upper plug portion, which may comprise a highly conductive...
US20050272254 Method of depositing low resistivity barrier layers for copper interconnects  
We have discovered a method of providing a thin approximately from about 2 Å to about 100 Å thick TaN seed layer, which can be used to induce the formation of alpha tantalum when tantalum is...
US20070007657 Methods for forming conductive vias in a substrate and electronic devices and systems including an at least partially reversed oxidation injury at an interface between a conductive via and a conductive interconnect structure  
Methods for forming conductive vias in a substrate include oxidizing at least a portion of a metallic structure that is exposed through an opening in a substrate to form an oxidation injury in the...
US20060189126 Method of forming semiconductor device having epitaxial contact plug connecting stacked transistors  
A method of forming an epitaxial contact plug in a semiconductor device comprises forming an insulating interlayer on a semiconductor substrate, forming a mushroom-shaped epitaxial plug in an...
US20070082480 ULTRA THIN FET  
Processes are described for forming very thin semiconductor die (1 to 10 microns thick) in which a thin layer of the upper surface of the wafer is processed with junction patterns and contacts...
US20140154879 METHODS OF FORMING INTERCONNECTS AND SEMICONDUCTOR STRUCTURES  
A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure...
US20110129995 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION  
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite...
US20070155166 METHOD AND APPARATUS FOR DEPOSITING COPPER WIRING  
A method of depositing copper wiring that includes at least one of the following. Transporting a semiconductor substrate with a damascene pattern into a first chamber. Substantially concurrently...
US20120223437 Semiconductor Device Comprising Metallization Layers of Reduced Interlayer Capacitance by Reducing the Amount of Etch Stop Materials  
Upon forming a complex metallization system, the parasitic capacitance between metal lines of adjacent metallization layers may be reduced by providing a patterned etch stop material. In this...
US20050110142 Diffusion barriers formed by low temperature deposition  
A solid state device includes a first material and a second material. A barrier layer is formed between the first material and the second material to prevent diffusion between the first material...
US20050170638 Method for forming dual damascene interconnect structure  
A method for forming dual damascene structures within a semiconductor device utilizes a plug material that is soluble in alkaline developers such as 2.38 wt % TMAH. The plug material is introduced...
US20080233735 Etching method for semiconductor element  
An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO)...
US20050260846 Substrate processing method, semiconductor device production method, and semiconductor device  
A substrate processing method is disclosed that, when forming a copper film on a miniaturized pattern with a copper diffusion prevention film being formed thereon, allows cleaning the copper...
US20070052106 Semiconductor device and method for fabricating the same  
A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one...
US20060024954 Copper damascene barrier and capping layer  
A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer;...
US20050093169 Semiconductor device and method of manufacturing semiconductor device  
A semiconductor device comprises a semiconductor substrate; a semiconductor element formed on a surface of said semiconductor substrate; and a stacked film which includes a plurality of interlayer...
US20070082479 Chemical mechanical polishing techniques for integrated circuit fabrication  
The present invention provides methods for fabricating horizontal interconnect lines for use in semiconductor wafer fabrication. A dielectric layer is deposited on a dielectric stack having a...
US20070052095 Semiconductor device and manufacturing method thereof  
Provided is a technology capable of improving the reliability of a semiconductor device using WPP by preventing a short-circuit failure between uppermost-level interconnects. In the present...
US20060183317 Semiconductor device and a method of manufacturing the same  
Provided are a semiconductor device comprising a semiconductor substrate, a first insulating film formed thereover, interconnects formed over the first insulating film and having copper as a main...
US20070284755 Semiconductor device, manufacturing method of the semiconductor device, and mounting method of the semiconductor device  
A semiconductor device, including a semiconductor substrate where a plurality of functional elements is formed; and a multilayer interconnection layer provided over the semiconductor substrate,...
US20050116333 Semiconductor device and semiconductor device manufacturing method  
Disclosed is a semiconductor device that includes: a semiconductor substrate; a first insulating film formed above the semiconductor substrate and having a relative dielectric constant of 3.8 or...
US20120032331 CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF  
A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are...
US20080102587 METHOD OF MANUFACTURING HIGH VOLTAGE DEVICE  
A method of manufacturing a high voltage device includes forming a junction region in a semiconductor substrate. An insulating layer is formed over the semiconductor substrate. A portion of the...
US20070045861 Semiconductor device, and production method for manufacturing such semiconductor device  
A semiconductor device has a semiconductor substrate, and a multi-layered wiring arrangement provided thereon. The multi-layered wring arrangement includes at least one insulating layer structure...

Matches 1 - 50 out of 67 1 2 >