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US20050208742 OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE PROCESSING  
A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting...
US20080054413 SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME  
A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top...
US20150162282 BI-LAYER HARD MASK FOR ROBUST METALLIZATION PROFILE  
A robust metallization profile is formed by forming two or more layers of hard mask with different density. Multi-layer metal hard mask is helpful especially in small feature size process, for...
US20060035457 Interconnection capacitance reduction  
An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the...
US20060001168 Technique for forming a dielectric interlayer above a structure including closely spaced lines  
By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces...
US20140038408 FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE  
A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via...
US20140038407 FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE  
A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via...
US20110281432 FLUORINE DEPLETED ADHESION LAYER FOR METAL INTERCONNECT STRUCTURE  
A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via...
US20130032945 SELF-ALIGNED FINE PITCH PERMANENT ON-CHIP INTERCONNECT STRUCTURES AND METHOD OF FABRICATION  
An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a...
US20090243101 METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT  
A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous...
US20060278954 Semiconductor device having interlayer insulating film covered with hydrogen diffusion barrier film and its manufacture method  
An interlayer insulating film made of insulating material is formed on a semiconductor substrate. A hydrogen diffusion barrier film is formed on the interlayer insulating film, the hydrogen...
US20140252648 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a...
US20060035458 Semiconductor element  
The invention relates to a semiconductor component having a semiconductor body (1), to which a metallization (10), which is formed from metallization layers (11, 13, 15, 17) and separating layers...
US20070243703 Processes and structures for epitaxial growth on laminate substrates  
A method of making a semiconductor device includes providing a laminate substrate made by bonding a II-VI or III-V semiconductor laminate film to a support substrate, and preparing the laminate...
US20060125102 Back end of line integration scheme  
A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal...
US20070013009 Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture  
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The...
US20100164074 Dielectric separator layer  
The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a...
US20050153539 Method of forming interconnection lines in a semiconductor device  
A method of forming interconnection lines in a semiconductor device is disclosed. According to the method, a trench is formed in a semiconductor substrate and a scattered reflection layer is...
US20080057701 METHOD FOR PREVENTION OF RESIST POISONING IN INTEGRATED CIRCUIT FABRICATION  
A method of manufacturing an integrated circuit comprising fabricating a dual damascene interconnect. Fabricating the interconnect including forming a via opening in a surface of an inter-layer...
US20070013012 Etch-stop layer structure  
A semiconductor structure that includes a first gate structure, second gate structure and a nitrogen-containing etch-stop layer. The first gate structure whose sidewalls are bounded by at least...
US20050173803 Interlayer adhesion promoter for low k materials  
The invention relates to the production of multilayered dielectric structures and to semiconductor devices and integrated circuits comprising these structures. The structures of the invention are...
US20060199371 SEMICONDUCTOR DEVICES PASSIVATION FILM  
A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first...
US20090008783 SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY  
A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed...
US20090001594 AIRGAP INTERCONNECT SYSTEM  
A method may comprise assembling a first dielectric ensemble that comprises a first dielectric layer exhibiting a first porosity, a second dielectric layer exhibiting a second porosity and a third...
US20150206844 INTEGRATED CIRCUITS HAVING GATE CAP PROTECTION AND METHODS OF FORMING THE SAME  
Integrated circuits and methods of forming integrated circuits are provided. An integrated circuit includes a gate electrode structure overlying a base substrate. The gate electrode structure...
US20120058637 SEMICONDUCTOR DEVICE MANUFACTURING METHOD  
A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect...
US20070105368 Method of fabricating a microelectronic device using electron beam treatment to induce stress  
The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure...
US20080203586 Integrated Circuit and Methods of Manufacturing a Contact Arrangement and an Interconnection Arrangement  
A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the...
US20110207316 Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same  
Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way...
US20070134910 High-dielectric sheet, a printed circuit board having the high-dielectric sheet and production methods thereof  
A high-dielectric sheet for a printed circuit board includes a first electrode, a first sputter film formed on the first electrode, an intermediate layer formed on the first sputter film by...
US20090085087 LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY  
A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over...
US20060099799 Plasma processing method and film forming method  
A plasma processing method of carrying out curing processing on a low dielectric constant film produced on a to-be-processed substrate by applying plasma thereto in a processing chamber of a...
US20080054470 Semiconductor Device and Method of Fabricating the Same  
The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the...
US20060172525 Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics  
In an etch process for forming via openings and trench openings in a low-k dielectric layer, the material removal of an underlying etch stop layer is decoupled from the etching through the low-k...
US20100270682 Implementing Vertical Airgap Structures Between Chip Metal Layers  
A method and structure are provided for implementing vertical airgap structures between chip metal layers. A first metal layer is formed. A first layer of silicon dioxide dielectric is deposited...
US20090315186 Method for manufacturing semiconductor device and the semiconductor device  
An etching stopper film is formed on top of a first insulating film. The etching stopper film is a film formed by depositing at least two films, made of constituent materials identical in quality...
US20070004193 Method for reworking low-k dual damascene photo resist  
A new method of forming a dual damascene structure involves forming a via-level precursor structure on a substrate and spin coating an oxide protective layer over the bottom anti-reflective...
US20070134911 Dual damascene process and method for forming a copper interconnection layer using same  
A method for forming a copper interconnection using a dual damascene process includes forming a second insulating layer on a first insulating layer, the first insulating layer including a lower...
US20070117373 THIN FILM MAGNETIC HEAD WITH A METAL LAMINATION PART AND METHOD OF MANUFACTURING THE SAME  
A thin film magnetic head with a metal lamination part and method of manufacturing the same are provided. The thin film magnetic head including a metal lamination part in which an upper metal...
US20140300005 MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME  
A multilevel interconnect structure for a semiconductor device includes an intermetal dielectric layer with funnel-shaped connecting vias. The funnel-shaped connecting vias are provided in...
US20080081460 Method of manufaturing a semiconductor device  
In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion...
US20060281301 Method for manufacturing dual damascene pattern  
Normal+Times New Roman, Justified, Line spacing: 1.5 lines A method for forming a dual damascene pattern is provided. According to the method, a diffusion barrier layer and an interlayer...
US20050095839 METHOD OF PATTERNING LOW-K FILM AND METHOD OF FABRICATING DUAL-DAMASCENE STRUCTURE  
A method of patterning a low-k film is provided. In this method, a dielectric layer is spun over a substrate, and then an electron-beam exposure process is performed on the dielectric layer to...
US20070281497 METHOD TO MITIGATE IMPACT OF UV AND E-BEAM EXPOSURE ON SEMICONDUCTOR DEVICE FILM PROPERTIES BY USE OF A BILAYER FILM  
Methods are provided for processing a substrate comprising a bilayer barrier film thereon. In one aspect, a method comprises depositing a first barrier layer, depositing a second barrier layer on...
US20070004194 Method for fabricating semiconductor device with deep opening  
A method for fabricating a semiconductor device with a deep opening is provided. The method includes: forming an insulation layer on a substrate; selectively etching the insulation layer to form...
US20050242435 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging  
The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides...
US20060180842 Capacitor, method of making the same, filter using the same, and dielectric thin film used for the same  
The capacitor (10) in accordance with the present invention comprises a lower electrode (14A), a dielectric layer (16) including an SiO2 layer (20) formed on the lower electrode (14A) and an Si3N4...
US20080233735 Etching method for semiconductor element  
An etching method for semiconductor element is provided. The etching method includes the following procedure. First, a to-be-etched substrate is provided. Then, a silicon-rich silicon oxide (SRO)...
US20140035146 METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying...
US20120309188 METHOD TO IMPROVE ADHESION FOR A SILVER FILLED OXIDE VIA FOR A NON-VOLATILE MEMORY DEVICE  
A method for forming an interconnect structure for a memory device. The method includes providing a partially fabricated device. The partially fabricated device includes a switching element...

Matches 1 - 50 out of 116 1 2 3 >