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US20140124877 CONDUCTIVE INTERCONNECT INCLUDING AN INORGANIC COLLAR  
A conductive interconnect includes an inorganic collar. The conductive interconnect includes a conductive support layer. The conductive interconnect also includes a conductive material on the...
US20140264924 APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND ELECTROMIGRATION AFFECTS  
An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of...
US20050006770 Copper-low-K dual damascene interconnect with improved reliability  
A dual damascene-based interconnect structure which includes a liner of aluminum-0.5% copper alloy. The alloy can be implemented by depositing the alloy using a conventional PVD technique. To...
US20140094028 Contact and Via Interconnects Using Metal Around Dielectric Pillars  
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect...
US20110165774 Contact and Via Interconnects Using Metal Around Dielectric Pillars  
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect...
US20110269307 Method for Making Integrated Circuit Device Using Copper Metallization on 1-3 PZT Composite  
Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au)...
US20120038054 IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS  
A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The...
US20130295764 METHOD FOR REDUCING DIELECTRIC OVERETCH WHEN MAKING CONTACT TO CONDUCTIVE FEATURES  
A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive...
US20110171823 DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME  
A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring...
US20140021611 Novel Copper Etch Scheme for Copper Interconnect Structure  
The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a...
US20110101534 AUTOMATED SHORT LENGTH WIRE SHAPE STRAPPING AND METHODS OF FABRICTING THE SAME  
An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length...
US20140145340 Flip Chip Interconnection Structure  
A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip,...
US20130200521 INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL  
Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature,...
US20120068174 ELECTRICAL MASK INSPECTION  
An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and...
US20060017153 Interconnections of semiconductor device and method of forming the same  
An interconnection structure includes a substrate containing a first lower interconnection and a pair of second interconnections separated from each other by a predetermined distance, and a...
US20080099877 DAMAGE PROPAGATION BARRIER AND METHOD OF FORMING  
A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse...
US20150054592 ON-CHIP VERTICAL THREE DIMENSIONAL MICROSTRIP LINE WITH CHARACTERISTIC IMPEDANCE TUNING TECHNIQUE AND DESIGN STRUCTURES  
A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically,...
US20080042268 Void boundary structures, semiconductor devices having the void boundary structures and methods of forming the same  
Void boundary structures, semiconductor devices having the void boundary structures, and methods of forming the same are provided. The structures, semiconductor devices and methods present a way...
US20060001163 Groundless flex circuit cable interconnect  
Embodiments of the present invention include an apparatus, method, and/or system for using a groundless flex circuit cable to interconnect semiconductor packages.
US20060292855 CURRENT-ALIGNED AUTO-GENERATED NON-EQUIAXIAL HOLE SHAPE FOR WIRING  
A method, system and program product for replacing isotropic hole shapes in a wiring layout with non-equiaxial hole shapes that are arranged in a direction of current flow, which increases current...
US20070042609 Molecular caulk: a pore sealant for ultra-low k dielectrics  
Methods of use of parylene based polymers with porous ultra-low κ dielectric materials and use of parylene barriers in integrated circuit fabrication are presented.
US20060024958 HSQ/SOG dry strip process  
A spin-on dielectric (120) strip process. Instead of a wet strip, a dry strip process is used to remove the spin-on dielectric (120). In a via-first dual damascene method, a via (116) may be...
US20080150152 Carbon nanotube-based interconnection element  
The present invention concerns an element designed to interconnect at least two conductors of a microelectronic circuit, including: an initial conductor (210), referred to as lower conductor;a...
US20050208779 Imprint lithography process  
An imprint lithography process is used for the production of a semiconductor component. A polymeric gate dielectric layer (12) is structured in the absence of a resist solely by at least one...
US20070164436 DUAL METAL INTERCONNECTION  
Embodiments relate to a dual metal interconnection structure of a semiconductor device and a method for manufacturing the same. In embodiments, the dual metal interconnection structure may include...
US20140306349 LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER  
Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and...
US20100330800 METHODS OF FORMING LAYERS OF ALPHA-TANTALUM  
A method of forming a layer of alpha-tantalum on a substrate including the steps of depositing a layer of titanium nitride on a substrate; and depositing a layer of alpha-tantalum on the layer of...
US20070010086 Circuit board with a through hole wire and manufacturing method thereof  
An aluminum substrate is drilled to form a first through hole, and is then laminated with copper foils on upper and lower surfaces of the aluminum substrate via a binder. Due to the pressure of...
US20080121982 Semiconductor structure, semiconductor memory device and method of manufacturing the same  
A semiconductor structure includes first and second conductive lines which cross each other. The second conductive lines are electrically insulated from the first conductive lines via an...
US20110095395 Inductors and Methods for Integrated Circuits  
Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on...
US20130026633 Multilayer Metallization with Stress-Reducing Interlayer  
A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 μm and an interlayer disposed in the multilayer metallization with a first...
US20110101347 Interconnect Sensor for Detecting Delamination  
An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed...
US20140151888 Air-Gap Formation in Interconnect Structures  
A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the...
US20110298026 LOGIC-BASED eDRAM USING LOCAL INTERCONNECTS TO REDUCE IMPACT OF EXTENSION CONTACT PARASITICS  
An electronic device includes an active layer located over a substrate with the active layer having a logic circuit and an eDRAM cell. The electronic device also includes a first metallization...
US20080079159 Focused stress relief using reinforcing elements  
In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold...
US20060024953 Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess  
A method for fabricating a barrier layer. A first barrier layer (124) is deposited over a dielectric (104) including in a trench (108) and via (106). A re-sputtering process is then performed to...
US20100052177 METHOD FOR MANUFACTURING A CROSSBAR CIRCUIT DEVICE  
Method for manufacturing a crossbar circuit on a substrate (1), the crossbar circuit comprising a first grid of first wires (10) and a second grid of second wires (17), the first wires extending...
US20100001370 INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS  
An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate;...
US20140374914 STRESS COMPENSATION PATTERNING  
An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage...
US20070123027 Wiring forming method, wiring forming apparatus, and wiring board  
After performing one forming step of a first pattern forming step of forming a first patent on a substrate and a second pattern forming step of forming a second pattern on the substrate, the other...
US20130005136 Methods Of Forming Metal Silicide-Comprising Material And Methods Of Forming Metal Silicide-Comprising Contacts  
A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second...
US20100155956 FILL PATTERNING FOR SYMMETRICAL CIRCUITS  
A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement...
US20140264880 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a...
US20050221603 System architecture of semiconductor manufacturing equipment  
Provided herein is a system architecture of semiconductor manufacturing equipment, wherein degas chamber(s) are integrated to the conventional pass-through chamber location. Also provided herein...
US20120168957 METHOD TO REDUCE DEPTH DELTA BETWEEN DENSE AND WIDE FEATURES IN DUAL DAMASCENE STRUCTURES  
A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and...
US20150206835 METHOD, STRUCTURES AND METHOD OF DESIGNING REDUCED DELAMINATION INTEGRATED CIRCUITS  
An integrated circuit wire structure. The structure includes a set of interconnect levels over a semiconductor substrate, each interconnect level of the set of interconnect levels comprising...
US20080023854 Generating an Integrated Circuit Identifier  
The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of least one conductive path by cutting the chip, the position of the cutting line...
US20070210453 Dummy-fill-structure placement for improved device feature location and access for integrated circuit failure analysis  
An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The...
US20100038790 RELIABILITY OF WIDE INTERCONNECTS  
An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the...
US20130292835 CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS  
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal...

Matches 1 - 50 out of 376 1 2 3 4 5 6 7 8 >