Match Document Document Title
US20140035135 SOLDER BUMP FOR BALL GRID ARRAY  
A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width...
US20130320524 Design Scheme for Connector Site Spacing and Resulting Structures  
A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second...
US20140291838 Design Scheme for Connector Site Spacing and Resulting Structures  
A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second...
US20130020698 Pillar Design for Conductive Bump  
A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches are used to channel conductive...
US20120112343 ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS  
Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least...
US20140021600 REDISTRIBUTION LAYER (RDL) WITH VARIABLE OFFSET BUMPS  
An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL...
US20140014959 PASSIVATION LAYER FOR PACKAGED CHIP  
A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first...
US20140084460 Contact bumps methods of making contact bumps  
Contact bumps between a contact pad and a substrate can include recesses and protrusions that can mate with the material of the substrate. The irregular mating surfaces between the contact bumps...
US20120261813 REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE  
Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections...
US20110230044 CONTACT STRUCTURE HAVING A COMPLIANT BUMP AND A TESTING AREA AND MANUFACTURING METHOD FOR THE SAME  
A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer...
US20150194396 BOND PAD HAVING A TRENCH AND METHOD FOR FORMING  
A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a...
US20060113667 Bond pad structure for gold wire bonding to copper low K dielectric silicon devices  
A bond pad structure which improves the reliability of the gold bonds, and thus, of the device. The bond pad structure allows for small gold bonds, which increases the density of the device. One...
US20140117532 Bump Interconnection Ratio for Robust CPI Window  
The disclosure is directed to a device and method for manufacture thereof. The device includes a first workpiece bonded to a second workpiece by a bump interconnection structure. The bump...
US20130149857 SOLDER INTERCONNECT BY ADDITION OF COPPER  
A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A...
US20110006415 SOLDER INTERCONNECT BY ADDITION OF COPPER  
A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A...
US20110317385 WAFER LEVEL PACKAGE (WLP) DEVICE HAVING BUMP ASSEMBLIES INCLUDING A BARRIER METAL  
WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper...
US20140327134 METAL BUMP STRUCTURE FOR USE IN DRIVER IC AND METHOD FOR FORMING THE SAME  
A metal bump structure for use in a driver IC includes a passivation layer disposed on a metal pad and defining a recess on the metal pad, an adhesion layer in said recess, on the metal pad and on...
US20140124920 STUD BUMP STRUCTURE AND METHOD FOR MANUFACTURING THE SAME  
A stud bump structure and method for manufacturing the same are provided. The stud bump structure includes a substrate, and a first silver alloy stud bump disposed on the substrate, wherein the...
US20150108642 STRUCTURE TO PREVENT SOLDER EXTRUSION  
A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond...
US20140077358 Bump Structure and Method of Forming Same  
An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a...
US20140327133 METAL BUMP STRUCTURE FOR USE IN DRIVER IC AND METHOD FOR FORMING THE SAME  
A metal bump structure for use in a driver IC includes a metal bump disposed on a matrix, an optional capping layer disposed on the metal bump to completely cover the metal bump and a protective...
US20110163442 METHOD OF MANUFACTURING A PLURALITY OF ICS AND TRANSPONDERS  
A method of manufacturing a plurality of ICs for different transponder types adapted for different operating range is provided, wherein the method comprises manufacturing a first IC having a first...
US20110201194 Direct IMS (Injection Molded Solder) Without a Mask for Forming Solder Bumps on Substrates  
An assembly is obtained; it includes a substrate; a plurality of wet-able pads formed on a surface of the substrate; and a solder resist layer deposited on the surface of the substrate and having...
US20140131865 Structure and Method for Bump to Landing Trace Ratio  
The present disclosure provides an integrated circuit. The integrated circuit includes an interconnect structure formed on a substrate; a landing metal trace formed on the interconnect structure...
US20130075907 Interconnection Between Integrated Circuit and Package  
In order to achieve finer bump interconnect pitch for integrated circuit packaging, while relieving pressure-induced delamination of upper layer dielectric films, the under bump metallurgy of the...
US20130299966 WSP DIE WITH OFFSET REDISTRIBUTION LAYER CAPTURE PAD  
A WSP die having a redistribution layer (“RDL”) with an RDL capture pad that has an RDL pad central axis RR and a RDL pad outer peripheral edge arranged about the RDL capture pad central axis RR...
US20060006533 Motherboard structure for preventing short circuit  
A motherboard for preventing short circuit includes an IC device and a PCB. The IC device has a plurality of tin balls, and the PCB has matching pads with the tin balls of the IC device. The tin...
US20130026626 METHOD FOR FORMING BUMPS AND SUBSTRATE INCLUDING THE BUMPS  
Disclosed herein are a method for forming bumps and a substrate including the bumps. The method includes: coating a solder resist on a substrate and electrodes formed on the substrate: performing...
US20110079895 BUMP STRUCTURE, CHIP PACKAGE STRUCTURE INCLUDING THE SAME AND METHOD OF MANUFACTURING THE SAME  
A bump structure includes a first substrate, a plurality of first bond pads, a plurality of dielectric bumps, a plurality of under bump metal layers, and a plurality of metal layers. The plurality...
US20140264841 Surface Treatment in Electroless Process for Adhesion Enhancement  
An embodiment method of forming and a bump structure are disclosed. The bump structure includes a passivation layer formed over a metal pad, the passivation layer having a recess exposing a...
US20140332953 CHIP ARRANGEMENT, AND METHOD FOR FORMING A CHIP ARRANGEMENT  
A chip arrangement may include: a chip including a plurality of electrical nets, wherein each electrical net includes at least one bonding pad; and a plurality of pillars formed on the at least...
US20140346513 Mixed-Sized Pillars That Are Probeable and Routable  
An integrated circuit with probeable and routable interfaces is disclosed. The integrated circuit includes multiple micro-pillars that are attached to the surface of the integrated circuit, and...
US20140077365 Metal Bump and Method of Manufacturing Same  
An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact...
US20130313705 IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK  
A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled...
US20130043583 Dummy Flip Chip Bumps for Reducing Stress  
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein...
US20130234316 SELF-ALIGNED POLYMER PASSIVATION/ALUMINUM PAD  
The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering...
US20140009219 DIE POWER STRUCTURE  
A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a...
US20130120054 DIE POWER STRUCTURE  
A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a...
US20120161856 DIE POWER STRUCTURE  
A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a...
US20150001706 SYSTEMS AND METHODS FOR AVOIDING PROTRUSIONS IN INJECTION MOLDED SOLDER  
A method includes positioning a solder mask on an integrated circuit (IC) package substrate with the solder mask having cavities that extend to the IC package substrate, applying molten solder to...
US20120007231 METHOD OF FORMING CU PILLAR CAPPED BY BARRIER LAYER  
A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper...
US20120178251 METHOD OF FORMING METAL PILLAR  
The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a...
US20140342545 Techniques for Fabricating Fine-Pitch Micro-Bumps  
Techniques for fabricating fine-pitch micro-bumps are disclosed. According to one embodiment, a fabrication process may comprise the following steps: depositing a dielectric layer on a wafer;...
US20140106560 DEBOND INTERCONNECT STRUCTURES  
The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion...
US20120280388 COPPER PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE AND METHOD OF MAKING THE SAME  
This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated...
US20130149856 Interface Structure for Copper-Copper Peeling Integrity  
An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers....
US20110133331 INTERFACE STRUCTURE FOR COPPER-COPPER PEELING INTEGRITY  
An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers....
US20150044864 COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP  
Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package....
US20130273730 METHOD TO REALIZE FLUX FREE INDIUM BUMPING  
A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump...
US20150179590 SUBSTRATE COMPRISING IMPROVED VIA PAD PLACEMENT IN BUMP AREA  
Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension....