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US20090102013 |
FUSE BOX AND METHOD OF FORMING THE SAME
A fuse box includes a fuse pattern having a rugged profile and an interlayer insulating film including a fuse blowing window to fill the fuse pattern. |
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US20100320561 |
Method for forming a one-time programmable metal fuse and related structure
According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure... |
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US20120286390 |
ELECTRICAL FUSE STRUCTURE AND METHOD FOR FABRICATING THE SAME
An electrical fuse structure includes a top fuse, a bottom fuse and a via conductive layer positioned between the top fuse and the bottom fuse for providing electric connection. The top fuse... |
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US20140065813 |
SIZE-FILTERED MULTIMETAL STRUCTURES
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A... |
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US20130082347 |
One Time Programmable Structure Using a Gate Last High-K Metal Gate Process
An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon... |
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US20140106559 |
SYSTEM AND METHOD FOR FORMING AN ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME
A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer... |
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US20130320488 |
SYSTEM AND METHOD FOR FORMING ALUMINUM FUSE FOR COMPATIBILITY WITH COPPER BEOL INTERCONNECT SCHEME
A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer... |
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US20080296726 |
Fuse Structure for Maintaining Passivation Integrity
A fuse structure (106) includes a patterned conductor disposed over a passivation layer (302), which is disposed over a substrate (110), such as, for example, an inter-layer dielectric layer of an... |
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US20110147853 |
Method of Forming an Electrical Fuse and a Metal Gate Transistor and the Related Electrical Fuse
The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy... |
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US20060163685 |
THERMO-MECHANICAL CLEAVABLE STRUCTURE
A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure... |
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US20130071998 |
Electrical Fuse With Metal Line Migration
An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first... |
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US20150004781 |
FORMING BEOL LINE FUSE STRUCTURE
In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline... |
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US20120146710 |
Fuse Device
Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device. |
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US20140367826 |
MAKING AN EFUSE
A wafer chip and a method of designing the chip is disclosed. A first fuse is formed having a first critical dimension and a second fuse having a second critical dimension are formed in a layer of... |
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US20140210040 |
ELECTRONIC FUSE LINE WITH MODIFIED CAP
An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap... |
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US20080036031 |
FUSE BOX FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first... |
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US20140021578 |
VERTICAL ELECTRONIC FUSE
An electronic fuse structure including a first Mx metal comprising a conductive cap, an Mx+1 metal located above the Mx metal, wherein the Mx+1 metal does not comprise a conductive cap, and a via,... |
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US20140070362 |
E-FUSE STRUCTURES AND METHODS OF MANUFACTURE
E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first... |
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US20120326269 |
E-FUSE STRUCTURES AND METHODS OF MANUFACTURE
E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first... |
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US20130241031 |
PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING
Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly... |
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US20080099877 |
DAMAGE PROPAGATION BARRIER AND METHOD OF FORMING
A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse... |
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US20090267180 |
SEMICONDUCTOR DEVICE HAVING A REDUCED FUSE THICKNESS AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device... |
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US20140183688 |
MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE
An electronic fuse structure including an Mx level including a first Mx metal, a second Mx metal, and an Mx cap dielectric above of the first and second Mx metal, an Mx+1 level above the Mx level,... |
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US20150048479 |
SELF-ALIGNED VIA FUSE
A method including forming a first via opening in a substrate, the first via opening is self-aligned to a first trench in the substrate, forming a second via opening in the substrate, the second... |
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US20140077334 |
Electronic Fuse Vias in Interconnect Structures
An electronic fuse and method for forming the same. Embodiments of the invention include e-fuses having a first metallization level including a metal structure, a second metallization level above... |
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US20080093705 |
SEMICONDUCTOR DEVICE PREVENTING BRIDGE BETWEEN FUSE PATTERN AND GUARD RING
A semiconductor device having a fuse structure that can prevent a bridge between a fuse pattern and a guard ring, and a method of fabricating the same are provided. The fuse pattern formed on a... |
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US20140252538 |
ELECTRONIC FUSE WITH RESISTIVE HEATER
A method of forming an electronic fuse including forming an Mx level including a first and a second Mx metal, forming a first Mx+1 dielectric above the Mx level, forming a conductive path on a... |
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US20080315354 |
FUSE FOR SEMICONDUCTOR DEVICE
Embodiments relate to a fuse for a semiconductor device. To maintain a stable blowing characteristic with a minimized applied current, the fuse includes a fuse line having a blowing characteristic... |
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US20140061851 |
METAL-VIA FUSE
The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a metal-via fuse. The metal-via fuse and a programming transistor form a one-time... |
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US20090045484 |
METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a... |
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US20120074520 |
ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME
A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material... |
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US20070298547 |
Semiconductor device having a composite passivation layer and method of manufacturing the same
A semiconductor device and a method of manufacturing the same are provided. The semiconductor device comprises a fuse bank with a fuse window, a pad area with a pad window, and a composite... |
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US20140124891 |
FUSE DEVICE
A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second... |
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US20110018091 |
FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE
A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an... |
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US20090250786 |
FUSE PART OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A fuse part of a semiconductor device includes an insulation layer over a substrate, and a fuse over the insulation layer, wherein the fuse includes a plurality of blowing pads for irradiating a... |
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US20120257435 |
NON-SALICIDE POLYSILICON FUSE
The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming... |
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US20120214301 |
STRUCTURE AND METHOD TO FORM E-FUSE WITH ENHANCED CURRENT CROWDING
An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to... |
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US20080020560 |
Method for manufacturing fuse box having vertically formed protective film
A method for manufacturing a fuse box of a semiconductor device includes forming an interlayer dielectric film over a semiconductor substrate including a given lower structure; forming a metal... |
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US20090001506 |
DUAL STRESS LINER EFUSE
A semiconductor fuse structure comprises an anode connected to a first end of a fuse link, a cathode connected to a second end of the fuse link opposite the first end of the fuse link, a... |
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US20090108398 |
Fuse of Semiconductor Device and Method for Forming the Same
A fuse in a semiconductor device includes: first and second fuse patterns, each being in the shape of a bar, separated from each other in a blowing region; first and second contact plugs... |
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US20120261793 |
ELECTRICAL FUSE AND METHOD OF MAKING THE SAME
An improved electrical-fuse (e-fuse) device including a dielectric layer having a first top surface, two conductive features embedded in the dielectric layer and a fuse element. Each conductive... |
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US20150028447 |
METHODS OF FORMING AN E-FUSE FOR AN INTEGRATED CIRCUIT PRODUCT AND THE RESULTING E-FUSE STRUCTURE
An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region... |
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US20090090993 |
SINGLE CRYSTAL FUSE ON AIR IN BULK SILICON
An integrated eFUSE device is formed by forming a silicon “floating beam” on air, whereupon the fusible portion of the eFUSE device resides. This beam extends between two larger, supporting... |
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US20080290456 |
Electrical Fuse With Metal Silicide Pipe Under Gate Electrode
An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and... |
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US20120289041 |
BALLASTED POLYCRYSTALLINE FUSE
A polycrystalline fuse includes a first layer of polycrystalline material on a substrate and a second layer of a silicide material on the first layer. The first and second layers are shaped to... |
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US20140239440 |
Thin Beam Deposited Fuse
A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a... |
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US20110256709 |
LEVEL POSTURE SENSING CHIP AND ITS MANUFACTURING METHOD, LEVEL POSTURE SENSOR
The present invention discloses a gas pendulum style level posture sensing chip and its manufacturing method and a level posture sensor. The gas pendulum style level posture sensing chip includes:... |
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US20080032493 |
Semiconductor device
A semiconductor device includes a fuse wire, a portion to be fused that overlies the fuse wire with an insulation film interposed therebetween, and a plug connecting the portion to be fused and... |
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US20150041950 |
CONDUCTOR WITH SUB-LITHOGRAPHIC SELF-ALIGNED 3D CONFINEMENT
A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised... |
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US20070222029 |
Semiconductor device having a fuse element
A portion to be melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the... |