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US20120288626 Templated Monolayer Polymerization and Replication  
A self-replicating monolayer system employing polymerization of monomers or nanoparticle ensembles on a defined template provides synthesis of two-dimensional single molecule polymers. Systems of...
US20120112186 TREATMENT OF GATE DIELECTRIC FOR MAKING HIGH PERFORMANCE METAL OXIDE AND METAL OXYNITRIDE THIN FILM TRANSISTORS  
Embodiments of the present invention generally include TFTs and methods for their manufacture. The gate dielectric layer in the TFT may affect the threshold voltage of the TFT. By treating the...
US20150064883 METHOD AND SYSTEM FOR MANUFACTURING A SEMI-CONDUCTING BACKPLANE  
Methods and systems to manufacture a semi-conducting backplane are described. According to one set of implementations, semi-conducting particles are positioned in a supporting material of the...
US20120286338 CONTROL OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACKS AND STRUCTURES FOR CMOS DEVICES  
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than...
US20140151636 SINGLE-WALLED CARBON NANOTUBES/QUANTUM DOT HYBRID STRUCTURES AND METHODS OF MAKING AND USE OF THE HYBRID STRUCTURES  
Briefly described, embodiments of the present disclosure relate to structures including single-walled carbon nanotube/quantum dot networks, devices including the structures, and methods of making...
US20080145982 ISOLATION SPACER FOR THIN SOI DEVICES  
A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the...
US20140283901 NANOSTRUCTURE, NANOSTRUCTURE FABRICATION METHOD, AND PHOTOVOLTAIC CELL INCORPORATING A NANOSTRUCTURE  
The application discloses a technique for fabricating gallium-arsenide-phosphorous (GaAsP) nanostructures using gallium-assisted (Ga-assisted) Vapour-Liquid-Solid (VLS) growth, i.e. without...
US20150179985 HYBRID ORGANIC/INORGANIC EUTECTIC SOLAR CELL  
A method is disclosed for making a hybrid solar cell comprising organic and inorganic materials on an inexpensive substrate, such as glass. The materials are deposited on the substrate at low...
US20130280893 METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING IMPRINT LITHOGRAPHY  
The present invention discloses a method for production of selective growth masks using imprint lithography. The method includes steps of: providing a sapphire substrate, forming a GaN layer, an...
US20050136625 Ultra-thin glass devices  
Techniques for fabricating devices including an ultra-thin glass and such devices are described. An ultra-thin glass substrate having a thickness less than or equal to 200 microns is fixed to a...
US20110180908 WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME  
A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from...
US20110108806 Method to Modify the Conductivity of Graphene  
A gated electrical device includes a non-conductive substrate and a graphene structure disposed on the non-conductive substrate. A metal gate is disposed directly on a portion of the graphene...
US20070278622 Gallium Nitride Device Substrate Contaning A Lattice Parameter Altering Element  
A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.
US20110108954 Growth of Planar Non-Polar M-Plane Gallium Nitride With Hydride Vapor Phase Epitaxy (HVPE)  
A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such...
US20100068869 METHOD FOR FABRICATING A MICRO-ELECTRONIC DEVICE EQUIPPED WITH SEMI-CONDUCTOR ZONES ON AN INSULATOR WITH A HORIZONTAL GE CONCENTRATION GRADIENT  
A method for the realization of a microelectronic device which includes at least one semi-conductor zone which rests on a support and which exhibits a Germanium concentration gradient in a...
US20120104547 LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE  
Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and...
US20130213462 AXIALLY-INTEGRATED EPITAXIALLY-GROWN TANDEM WIRE ARRAYS  
A photoelectrode, methods of making and using, including systems for water-splitting are provided. The photoelectrode can be a semiconducting material having a photocatalyst such as nickel or...
US20120175741 Method for Direct Deposition of a Germanium Layer  
The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a...
US20130280894 METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING UNDERFILL DISPENSING AND SINTERING  
The present invention discloses a method for production of selective growth masks using underfill dispensing and sintering. The method includes steps of: providing a sapphire substrate, growing a...
US20110089427 SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF  
The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In...
US20110073834 ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION  
A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a...
US20100012972 Silicon-Germanium Hydrides and Methods for Making and Using Same  
The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds.
US20130270583 METHOD OF FORMING COPPER WIRING AND METHOD OF MANUFACTURING DISPLAY DEVICE  
A method of forming a copper wiring includes forming a copper film on a substrate; forming a resist on the copper film in accordance with a predetermined pattern; forming an oxide film on the...
US20100044836 PROCESS FOR PRODUCING LOCALISED Ge0I STRUCTURES, OBTAINED BY GERMANIUM CONDENSATION  
The invention relates to a process for making at least one GeOI structure by germanium condensation of a SiGe layer supported by a layer of silicon oxide. The layer of silicon oxide is doped with...
US20120280276 Single Crystal Ge On Si  
A single crystal germanium-on-silicon structure includes a single crystal silicon substrate. A single crystal layer of gadolinium oxide is epitaxially grown on the substrate. The gadolinium oxide...
US20090114955 Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure  
A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction...
US20120138886 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES  
Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to...
US20080173902 SOLID STATE IMAGING APPARATUS, IMAGING APPARATUS AND SOLID STATE IMAGING APPARATUS MANUFACTURING METHOD  
A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light...
US20110260283 DIELECTRIC COMPOSITION FOR THIN-FILM TRANSISTORS  
An electronic device, such as a thin-film transistor, includes a substrate and a dielectric layer formed from a dielectric composition. The dielectric composition includes a dielectric material, a...
US20090242987 DOUBLE-GATE SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS AND METHODS OF MANUFACTURE THEREOF  
A double-gate FinFET and methods for its manufacture are provided. The FinFET includes first and second gates (72, 74) adjacent respective sides of the fin (20), with at least a portion of the...
US20090220782 Method of Forming Gallium Arsenide-On-Insulator  
A method of forming gallium arsenide (GaAs)-on-insulator includes providing a substrate and forming a diffusion barrier layer of a compound of formula AlxGa1-xAs on the substrate. A layer of GaAs...
US20090294749 Chemical Mechanical Polishing Slurry Composition for Polishing Phase-Change Memory Device and Method for Polishing Phase-Change Memory Device Using the Same  
A slurry composition for chemical mechanical polishing (CMP) of a phase-change memory device is provided. The slurry composition comprises deionized water and iron or an iron compound. The slurry...
US20060194417 Polycrystalline sillicon substrate  
A polycrystalline silicon substrate for a solar cell formed by growing a high purity polycrystalline silicon layer on a surface of a base obtained by slicing a polycrystalline silicon ingot...
US20130099357 STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON  
A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate...
US20090065786 PROCESS FOR PRODUCING THIN NITRIDE FILM ON SAPPHIRE SUBSTRATE AND THIN NITRIDE FILM PRODUCING APPARATUS  
A method for growing a nitride thin film on a sapphire substrate, in which using no resists, miniaturization can be accomplished while relieving vexatious complication of the process; and a...
US20130072003 SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE  
Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed...
US20120305992 HYBRID MONOLITHIC INTEGRATION  
The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the...
US20110156004 Multi-gate III-V quantum well structures  
Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate...
US20140191319 FINFET COMPATIBLE DIODE FOR ESD PROTECTION  
A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and...
US20130015426 METHOD OF MANUFACTURING OF A SEMI-CONDUCTOR ELEMENT AND SEMI-CONDUCTOR ELEMENT  
A method of manufacturing of a semi-conductor element, comprising the following steps: providing a substrate, the substrate having a surface, the surface being partially coated with a coating and...
US20070298592 Method for manufacturing single crystalline gallium nitride material substrate  
A gallium nitride substrate is originally grown above a silicon substrate. The present invention easily separates the gallium nitride substrate from the silicon substrate. And the separation is...
US20120258584 GLASS SUBSTRATE COMPRISING AN EDGE WEB PORTION  
A glass ribbon coated with a flexible material, the flexible coating forming a flexible web portion that extends from an edge of the glass ribbon at least one millimeter. The flexible web portion...
US20140299975 Method and Board for Growing High-Quality Graphene Layer Using High Pressure Annealing  
This invention relates to a method and board for forming a graphene layer, and more particularly, to a method of forming a high-quality graphene layer using high pressure annealing and to a board...
US20090250791 Crystalline Semiconductor Stripes  
Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator...
US20080050857 Group III nitride coatings and methods  
The invention provides a composition that is a dispersion made from a Group III nitride, a solvent system, and a dispersant. The dispersion can be used to prepare Group III nitride thin films on a...
US20080157171 DIELECTRIC BARRIER FOR NANOCRYSTALS  
Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating...
US20140061590 GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME  
The method of manufacturing a graphene device includes forming an insulating material layer on a substrate, forming first and second metal pads on the insulating material layer spaced apart from...
US20120199812 STRAIN TUNABLE SILICON AND GERMANIUM NANOWIRE OPTOELECTRONIC DEVICES  
Silicon, silicon-germanium alloy, and germanium nanowire optoelectronic devices and methods for fabricating the same are provided. According to one embodiment, a P-I-N device is provided that...
US20070141812 Low temperature doped silicon layer formation  
A doped silicon layer is formed in a batch process chamber at low temperatures. The silicon precursor for the silicon layer formation is a polysilane, such as trisilane, and the dopant precursor...
US20050186764 Method for lifting offGaN pseudomask epitaxy layerusing wafer bonding way  
Present invention is a method for lifting off GaN pseudomask epitaxy layer using wafer bonding way, wherein GaN epitaxy is obtained by way of selective area growth on a seed and the growth is in a...