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US20050142991 |
Substrate polishing apparatus
A substrate polishing apparatus is provided for preventing excessive polishing and insufficient polishing, and enabling a quantitative setting of an additional polishing time. The substrate... |
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US20070132056 |
Isolation structures for semiconductor integrated circuit substrates and methods of forming the same
Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the... |
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US20050239265 |
Method of forming trench isolation regions
In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench... |
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US20060234469 |
A method of forming semiconductor structures
In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer... |
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US20060183296 |
Isolation method for semiconductor device
An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor... |
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US20150270375 |
METHOD OF MANUFACTURE FOR A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The... |
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US20080113483 |
Methods of etching a pattern layer to form staggered heights therein and intermediate semiconductor device structures
A method of forming staggered heights in a pattern layer of an intermediate semiconductor device structure. The method comprises providing an intermediate semiconductor device structure comprising... |
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US20070212850 |
GAP-FILL DEPOSITIONS IN THE FORMATION OF SILICON CONTAINING DIELECTRIC MATERIALS
A chemical vapor deposition method for forming a dielectric material in a trench formed on a substrate, where the method includes the steps of generating water vapor by contacting hydrogen gas and... |
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US20060125024 |
Semiconductor device and a method of manufacturing the same
To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the... |
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US20050191823 |
Polishing composition and polishing method
A polishing composition includes more than 0.1% by mass of colloidal silica, and water, and has a pH of 6 or less. The polishing composition has the ability to polish a titanium material at a high... |
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US20070134884 |
Isolation method of defining active fins, method of fabricating semiconductor device using the same and semiconductor device fabricated thereby
An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a... |
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US20070111467 |
Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
Provided are a method for forming a trench using a hard mask with high selectivity and an isolation method for a semiconductor device using the same. The method includes: forming a first hard mask... |
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US20080145989 |
SEMICONDUCTOR DEVICE HAVING PARTIALLY INSULATED FIELD EFFECT TRANSISTOR (PiFET) AND METHOD OF FABRICATING THE SAME
Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by... |
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US20070059897 |
Isolation for semiconductor devices
Methods of forming and structures for isolation structures for semiconductor devices are disclosed. The isolation structures are wider at the bottom than at the top, providing the ability to... |
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US20130200484 |
PROCESS FOR MANUFACTURING A WAFER BY ANNEALING OF BURIED CHANNELS
A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the... |
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US20120168858 |
NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A method of fabricating a non-volatile memory device includes providing a substrate with a cell region where a plurality of memory cells that are stacked vertically are to be formed and a... |
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US20100052019 |
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries... |
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US20070194403 |
Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods
Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls... |
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US20070161206 |
Isolation structure for strained channel transistors
A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a... |
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US20070040235 |
Dual trench isolation for CMOS with hybrid orientations
The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of... |
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US20060035437 |
Semiconductor device having dual-STI and manufacturing method thereof
A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of... |
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US20120208345 |
METHOD FOR FORMING A SELF-ALIGNED ISOLATION STRUCTURE UTILIZING SIDEWALL SPACERS AS AN ETCH MASK AND REMAINING AS A PORTION OF THE ISOLATION STRUCTURE
The present invention relates to methods for forming microelectronic structures in a semiconductor substrate. The method includes selectively removing dielectric material to expose a portion of an... |
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US20100270668 |
Dual Interconnection in Stacked Memory and Controller Module
A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of... |
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US20070207590 |
Manufacturing method of semiconductor device
According to an aspect of the invention, there is provided a manufacturing method of a semiconductor device including forming an isolation trench in a semiconductor substrate, filling an... |
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US20060151855 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a semiconductor substrate including an isolation trench provided on a surface thereof, an isolation film provided in the isolation trench, the isolation film... |
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US20090023265 |
ETCHING SOLUTION FOR REMOVAL OF OXIDE FILM, METHOD FOR PREPARING THE SAME, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
Provided are an anionic surfactant-containing etching solution for removal of an oxide film, preparation methods thereof, and methods of fabricating a semiconductor device using the etching... |
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US20050074949 |
Semiconductor device and a method for fabricating the semiconductor device
A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the... |
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US20070178664 |
SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FABRICATING THE SAME
A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP)... |
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US20080299739 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a first insulating film over a rear surface of a plurality of silicon substrates, annealing... |
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US20070087522 |
Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner
A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is... |
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US20070020877 |
Shallow trench isolation structure and method of fabricating the same
A shallow trench isolation structure has a trench formed in a substrate, a silicon oxynitride layer conformally formed on the sidewalls and bottom of the trench, and a high density plasma (HDP)... |
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US20150340274 |
METHODS FOR PRODUCING INTEGRATED CIRCUITS WITH AN INSULTATING LAYER
Methods for producing integrated circuits are provided. A method for producing an integrated circuit includes forming an insulating layer overlying a substrate, where the insulating layer is... |
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US20150206759 |
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is... |
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US20130316515 |
METHOD FOR PRODUCING SILICON DIOXIDE FILM
[Problem] To provide a method capable of forming an insulating film suffering less from both shrinkage and stress. [Means for solving] A method for forming a silicon dioxide film, comprising the... |
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US20090321834 |
Substrate fins with different heights
A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. |
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US20070117347 |
Semiconductor constructions
The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the opening can be protected with a liner... |
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US20120315738 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a method of manufacturing a semiconductor device. An insulating-separating portion, which surrounds an electrode penetrating a substrate, is filled with a stacked... |
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US20120021581 |
SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE
By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate... |
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US20110034005 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin... |
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US20100003802 |
METHOD FOR FABRICATING FIN TRANSISTOR
A method for fabricating a fin transistor includes patterning a first pad layer provided over a substrate using an isolation mask, etching the substrate using the isolation mask and the first pad... |
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US20070235783 |
Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over... |
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US20110260245 |
Cost Effective Global Isolation and Power Dissipation For Power Integrated Circuit Device
An integrated circuit device and method for fabricating the integrated circuit device is disclosed. In an embodiment, an apparatus includes a substrate having a first surface and a second surface,... |
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US20100285654 |
SEMICONDUCTOR DEVICE HAVING REDUCED DIE-WARPAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the... |
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US20080233709 |
METHOD FOR REMOVING MATERIAL FROM A SEMICONDUCTOR
A method for removing a material from a trench in a semiconductor. The method includes placing the semiconductor in a vacuum chamber, admitting a reactant into the chamber at a pressure to form a... |
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US20050221579 |
Semiconductor device and method of fabricating the same
A semiconductor device includes a semiconductor substrate and first and second trenches. The first trench with a high aspect ratio is formed in a surface of the semiconductor substrate and has a... |
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US20110147848 |
Multiple transistor fin heights
The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming transistor fins of differing heights... |
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US20060057815 |
Method of manufacturing a semiconductor device
In a method of manufacturing a high-voltage semiconductor device, a mask layer is formed on a semiconductor substrate. The mask layer is patterned to form a stepped portion of the mask layer. A... |
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US20050023634 |
Method of fabricating shallow trench isolation structure and microelectronic device having the structure
Provided is a method of fabricating a shallow trench isolation (STI) structure having a high aspect ratio and improved insulating properties. The exemplary method includes filling a shallow trench... |
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US20140315371 |
METHODS OF FORMING ISOLATION REGIONS FOR BULK FINFET SEMICONDUCTOR DEVICES
One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that... |
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US20130330908 |
SEMICONDUCTOR COMPONENT WITH VERTICAL STRUCTURES HAVING A HIGH ASPECT RATIO AND METHOD
A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control... |