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US20130075820 Superior Integrity of High-K Metal Gate Stacks by Forming STI Regions After Gate Metals  
When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, superior process robustness, reduced yield loss and an enhanced degree of flexibility in...
US20130069160 TRENCH ISOLATION STRUCTURE  
A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and...
US20090317957 Method for Forming Isolation Structures  
A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart...
US20150097224 BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS  
A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a...
US20130099281 POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION  
Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The...
US20150008528 DIFFUSION BARRIER AND METHOD OF FORMATION THEREOF  
A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and...
US20060063338 Shallow trench isolation depth extension using oxygen implantation  
The present invention is directed to structures and fabrication methods used to construct an improved shallow trench isolation structure are disclosed. The method involves providing a...
US20120235245 SUPERIOR INTEGRITY OF HIGH-K METAL GATE STACKS BY REDUCING STI DIVOTS BY DEPOSITING A FILL MATERIAL AFTER STI FORMATION  
When forming sophisticated semiconductor devices on the basis of high-k metal gate electrode structures, which are to be provided in an early manufacturing stage, the encapsulation of the...
US20090250770 INTEGRATION OF A SENSE FET INTO A DISCRETE POWER MOSFET  
A semiconductor device includes a main field effect transistor (FET) and one or more sense FETs, and a common gate pad. The main FET and the one or more sense FETs are formed in a common...
US20050158963 Method of forming planarized shallow trench isolation  
Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments...
US20150194497 METHOD OF FORMING CHANNEL OF GATE STRUCTURE  
A method of forming a channel of a gate structure is provided. A first epitaxial channel layer is formed within a first trench of the gate structure. A dry etching process is performed on the...
US20070093030 Reduction of boron diffusivity in pfets  
A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer) of semiconductor material provides a change from tensile to compressive stress in the...
US20070249129 STI stressor integration for minimal phosphoric exposure and divot-free topography  
A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on...
US20140342524 INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD  
An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion...
US20150145000 INTEGRATED CIRCUITS WITH SHALLOW TRENCH ISOLATIONS, AND METHODS FOR PRODUCING THE SAME  
Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate,...
US20090159981 STRAIN MODULATION IN ACTIVE AREAS BY CONTROLLED INCORPORATION OF NITROGEN AT Si-SiO2 INTERFACE  
Adding nitrogen to the Si—SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been problematic due to loss of the nitrogen...
US20150050792 EXTRA NARROW DIFFUSION BREAK FOR 3D FINFET TECHNOLOGIES  
Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride...
US20140256107 High Gate Density Devices and Methods  
A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming...
US20120091530 Low trigger voltage electrostatic discharge NFET in triple well CMOS technology  
An electrostatic discharge (ESD) protection device for an integrated circuit includes a buried layer of a first polarity type formed in a substrate of a second polarity type. A well region of the...
US20120146152 METHOD OF FABRICATING AN INTEGRATED CIRCUIT HAVING A STRAIN INDUCING HOLLOW TRENCH ISOLATION REGION  
A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill...
US20100163988 HIGH VOLTAGE (>100V) LATERAL TRENCH POWER MOSFET WITH LOW SPECIFIC-ON-RESISTANCE  
In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain...
US20050095808 Thermal oxidation method for topographic feature corner rounding  
Within a method for forming a topographic feature within a microelectronic substrate employed within a microelectronic fabrication, there is employed an oxidation mask layer sequentially as: (1)...
US20080258239 METHODS FOR MANUFACTURING A TRENCH TYPE SEMICONDUCTOR DEVICE HAVING A THERMALLY SENSITIVE REFILL MATERIAL  
Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to...
US20090098702 Method to Form CMOS Circuits Using Optimized Sidewalls  
A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed...
US20080217703 HIGHLY SELECTIVE LINERS FOR SEMICONDUCTOR FABRICATION  
A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a...
US20080150037 Selective STI Stress Relaxation Through Ion Implantation  
A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent...
US20140246720 INTEGRATED CIRCUIT PROTECTED FROM SHORT CIRCUITS CAUSED BY SILICIDE  
An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor...
US20080081404 Recessed STI for wide transistors  
A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask,...
US20140151759 FACET-FREE STRAINED SILICON TRANSISTOR  
The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during...
US20090224335 FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT  
Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow...
US20130001695 UNI-DIRECTIONAL TRANSIENT VOLTAGE SUPPRESSOR (TVS)  
An epitaxial layer is supported on top of a substrate. First and second body regions are formed within the epitaxial layer separated by a predetermined lateral distance. Trigger and source regions...
US20090072319 SEMICONDUCTOR DEVICE WITH RELATIVELY HIGH BREAKDOWN VOLTAGE AND MANUFACTURING METHOD  
A semiconductor device includes at least one active component (18) having a p-n junction (26) on the semiconductor substrate in an active region (19) of the semiconductor substrate (4). A shallow...
US20140103440 I-SHAPED GATE ELECTRODE FOR IMPROVED SUB-THRESHOLD MOSFET PERFORMANCE  
Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and...
US20080315268 Methods and Apparatus for Semiconductor Memory Devices Manufacturable Using Bulk CMOS Process Manufacturing  
The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred...
US20090258468 MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION STRESS  
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate...
US20060216935 Composition for oxide CMP in CMOS device fabrication  
The present invention provides an oxide CMP slurry composition for use in planarizing silicon oxide-containing films via CMP during CMOS device fabrication, and a method of planarizing silicon...
US20140141587 TRANSISTOR WITH IMPROVED SIGMA-SHAPED EMBEDDED STRESSOR AND METHOD OF FORMATION  
A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is...
US20100068859 METHOD OF MANUFACTURING A FET GATE  
A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region 8, and then forming a plurality of metallic layers 16, 18, 20 on gate dielectric 6 by...
US20080111197 SEMICONDUCTOR DEVICE INCLUDING A MISFET HAVING DIVIDED SOURCE/DRAIN REGIONS  
A MISFET includes source/drain regions each including a plurality of divided substrate regions divided by intervening insulation films, and a selectively-grown silicon layer formed on the divided...
US20090321836 DOUBLE GATE AND TRI-GATE TRANSISTOR FORMED ON A BULK SUBSTRATE AND METHOD FOR FORMING THE TRANSISTOR  
Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas,...
US20100044780 TRANSISTOR WITH GAIN VARIATION COMPENSATION  
A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned...
US20060068554 Process for etching trenches in an integrated optical device  
The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated...
US20120264268 METHODS OF FORMING ELECTRICAL ISOLATION REGIONS BETWEEN GATE ELECTRODES  
Methods of forming nonvolatile memory devices include forming first and second floating gate electrodes of first and second nonvolatile memory cells, respectively, at side-by-side locations on a...
US20080067612 Semiconductor Device Including Nickel Alloy Silicide Layer Having Uniform Thickness and Method of Manufacturing the Same  
A semiconductor device including a nickel alloy silicide layer having a uniform thickness includes isolation regions formed in a substrate, gate electrodes respectively formed on the substrate...
US20150064871 Forming Source/Drain Zones with a Delectric Plug Over an Isolation Region Between Active Regions  
An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion...
US20100148248 SEMICONDUCTOR DEVICE HAVING GATE TRENCHES AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first gate trench, a second gate trench, and a dummy gate trench provided in an active region extending in an X direction; and a first gate electrode, a second...
US20140197411 METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETROGRADE WELL FIELD EFFECT TRANSISTOR AND RESULTING DEVICE  
A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the...
US20140264444 STRESS-ENHANCING SELECTIVE EPITAXIAL DEPOSITION OF EMBEDDED SOURCE AND DRAIN REGIONS  
Shallow trench isolation structures are formed within a semiconductor layer of a substrate to define an active area. The active area is recessed relative to a top surface of the shallow trench...
US20110049620 Method for fabricating a MOS transistor with source/well heterojunction and related structure  
According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a...
US20070145495 Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performance  
A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing...

Matches 1 - 50 out of 223 1 2 3 4 5 >