Match Document Document Title
US20130217197 INTEGRATION TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC FOR SELECT GATE AND REPLACEMENT GATE FOR LOGIC  
A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer...
US20130023098 MANUFACTURING METHOD FOR METAL GATE  
A manufacturing method for a metal gate includes providing a substrate having a dielectric layer and a polysilicon layer formed thereon, the polysilicon layer, forming a protecting layer on the...
US20120292720 METAL GATE STRUCTURE AND MANUFACTURING METHOD THEREOF  
A metal gate structure includes a high dielectric constant (high-K) gate dielectric layer, a metal gate having at least a U-shaped work function metal layer positioned on the high-K gate...
US20120032280 MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS  
A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON...
US20130009257 REPLACEMENT METAL GATE WITH A CONDUCTIVE METAL OXYNITRIDE LAYER  
A disposable gate structure and a gate spacer are formed on a semiconductor substrate. A disposable gate material portion is removed and a high dielectric constant (high-k) gate dielectric layer...
US20120015488 HIGH-K GATE DIELECTRIC OXIDE  
A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate...
US20150171100 PROCESS FOR FORMING EDGE WORDLINE IMPLANTS ADJACENT EDGE WORDLINES  
A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first...
US20120326243 TRANSISTOR HAVING ALUMINUM METAL GATE AND METHOD OF MAKING THE SAME  
A transistor having an aluminum metal gate includes a substrate, a high-k gate dielectric layer, an aluminum metal gate and a source/drain region. The high-k gate dielectric layer is disposed on...
US20120119204 Replacement Gate Having Work Function at Valence Band Edge  
Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a...
US20110014767 LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS  
A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from...
US20110127590 INCREASING STABILITY OF A HIGH-K GATE DIELECTRIC OF A HIGH-K GATE STACK BY AN OXYGEN RICH TITANIUM NITRIDE CAP LAYER  
In a replacement gate approach, the oxygen contents of a cap material may be increased, thereby providing more stable characteristics of the cap material itself and of the high-k dielectric...
US20140363942 Method for forming a low resistivity tungsten silicide layer for metal gate stack applications  
Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be...
US20070018214 Magnesium titanium oxide films  
Embodiments of a magnesium titanium oxide structure on a substrate provide a dielectric for use in a variety of electronic devices. Embodiments of methods of fabricating such a dielectric include...
US20110207280 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC  
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two...
US20100320547 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC  
A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two...
US20130164897 TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME  
Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a...
US20110198708 TRANSISTORS HAVING ARGON GATE IMPLANTS AND METHODS OF FORMING THE SAME  
Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a...
US20050277256 Nanolaminates of hafnium oxide and zirconium oxide  
A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than...
US20150097252 SIMPLIFIED GATE-FIRST HKMG MANUFACTURING FLOW  
When forming field effect transistors according to the gate-first HKMG approach, the cap layer formed on top of the gate electrode had to be removed before the silicidation step, resulting in...
US20140291747 Tungsten Salicide Gate Source For Vertical NAND String To Control On Current And Cell Pillar Fabrication  
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer...
US20120045880 METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME  
A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a...
US20110159656 METHOD FOR MANUFACTURING A MOSFET WITH A SURROUNDING GATE OF BULK SI  
A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO2...
US20090004801 Method of forming lutetium and lanthanum dielectric structures  
Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the...
US20150108590 ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR  
Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally...
US20100276748 METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES  
Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the...
US20110042759 SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE  
A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the...
US20120056249 INTERLAYER FOR ELECTRONIC DEVICES  
Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as interlayers applied...
US20090261406 USE OF SILICON-RICH NITRIDE IN A FLASH MEMORY DEVICE  
A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes...
US20150072498 NON-PLANAR III-V FIELD EFFECT TRANSISTORS WITH CONFORMAL METAL GATE ELECTRODE & NITROGEN DOPING OF GATE DIELECTRIC INTERFACE  
A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a...
US20070272990 DIFFUSION TUBE, DOPANT SOURCE FOR A DIFFUSION PROCESS AND DIFFUSION METHOD USING THE DIFFUSION TUBE AND THE DOPANT SOURCE  
According to an exemplary embodiment of the present invention, a diffusion tube includes a diffusion housing which includes a first cavity within a first end which receives a diffusion target, a...
US20120156837 Sacrificial Spacer Approach for Differential Source/Drain Implantation Spacers in Transistors Comprising a High-K Metal Gate Electrode Structure  
In complex semiconductor devices, the profiling of the deep drain and source regions may be accomplished individually for N-channel transistors and P-channel transistors without requiring any...
US20080025084 High aspect ration bitline oxides  
A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least...
US20110223756 Method of Enhancing Photoresist Adhesion to Rare Earth Oxides  
A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS...
US20120319206 INTEGRATED CIRCUIT COMPRISING AN ISOLATING TRENCH AND CORRESPONDING METHOD  
An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion...
US20080261368 WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES  
Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate...
US20090303794 Structure and Method of A Field-Enhanced Charge Trapping-DRAM  
A field-enhanced (FE) charge trapping-DRAM (TDRAM) device is described which is suitable for DRAM applications, and for additional applications with lower power requirements. In some embodiments,...
US20150162414 SANDWICH SILICIDATION FOR FULLY SILICIDED GATE FORMATION  
When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material,...
US20140167137 High Voltage Gate Formation  
Embodiments described herein generally relate to methods of manufacturing charge-trapping memory by patterning the high voltage gates before other gates are formed. One advantage of such an...
US20120122283 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE  
A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on...
US20130075831 METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER  
A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a...
US20130020656 HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION  
Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k...
US20100109098 GATE STRUCTURE INCLUDING MODIFIED HIGH-K GATE DIELECTRIC AND METAL GATE INTERFACE  
A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is...
US20090059675 Radiation hardened multi-bit sonos non-volatile memory  
In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+...
US20140252492 GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS  
A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between...
US20150091079 NON-VOLATILE MEMORY (NVM) AND HIGH-K AND METAL GATE INTEGRATION USING GATE-FIRST METHODOLOGY  
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer...
US20150206949 TRANSISTORS AND FABRICATION METHODS THEREOF  
A method is provided for fabricating transistors. The method includes providing a substrate; and forming at least one dummy gate structure having a dummy gate dielectric layer and a dummy gate...
US20090101963 SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS  
Methods of forming a memory cell containing two split sub-lithographic charge storage nodes on a semiconductor substrate are provided. The methods can involve forming two split sub-lithographic...
US20120282748 Method for manufacturing stack structure of PMOS device and adjusting gate work function  
The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or...
US20050233530 Enhanced gate structure  
A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer...
US20140264542 MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER  
Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over...