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US20150126004 Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric  
A method of fabricating a FET device is provided that includes the following steps. A wafer is provided. At least one active area is formed in the wafer. A plurality of dummy gates is formed over...
US20150008490 Fluctuation Resistant FinFET  
This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it...
US20130302960 One-Time Programmable Device  
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a...
US20130020614 DUAL-GATE NORMALLY-OFF NITRIDE TRANSISTORS  
A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the...
US20150017775 Device with a Vertical Gate Structure  
A device includes a wafer substrate, a conical frustum structure formed in the wafer substrate, and a gate all-around (GAA) structure circumscribing the middle portion of the conical frustum...
US20130214352 Dual Gate Lateral MOSFET  
A dual gate lateral MOSFET comprises a drift region over a substrate, an isolation region formed in the drift region and a channel region formed in the drift region. The dual gate lateral MOSFET...
US20140253218 Multi-Gate Field Effect Transistor  
An improved field effect transistor (FET) is provided by segmenting the gates of a power FET wherein a controller can “decide” how much of the FET to use, thus increasing efficiency.
US20130082325 One-Time Programmable Device Having an LDMOS Structure and Related Method  
According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a...
US20150118814 FinFET with Trench Field Plate  
An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad...
US20100320541 METHOD FOR FABRICATING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE  
A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first...
US20140264280 NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS  
A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order...
US20140117425 INTERLAYER DIELECTRIC FOR NON-PLANAR TRANSISTORS  
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by...
US20100317167 METHOD FOR MAKING ASYMMETRIC DOUBLE-GATE TRANSISTORS BY WHICH ASYMMETRIC AND SYMMETRIC DOUBLE-GATE TRANSISTORS CAN BE MADE ON THE SAME SUBSTRATE  
A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block...
US20140319609 FINFET DRIVE STRENGTH MODIFICATION  
A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the...
US20120161230 MOS TRANSISTOR AND FABRICATION METHOD THEREOF  
A disclosed MOS transistor has a drain region offset from a gate electrode structure, wherein the gate electrode structure includes at least a first gate electrode and a second gate electrode such...
US20140080276 Technique For Forming A FinFET Device  
A three-dimensional structure disposed on a substrate is processed so as to alter the etch rate of material disposed on at least one surface of the structure. In some embodiments, a conformal...
US20150221726 FINFET WITH ISOLATED SOURCE AND DRAIN  
A FinFET has shaped epitaxial structures for the source and drain that are electrically isolated from the substrate. Shaped epitaxial structures in the active region are separated from the...
US20140099764 GRAPHENE DEVICE INCLUDING A PVA LAYER OR FORMED USING A PVA LAYER  
An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a...
US20150118809 METHOD OF MAKING STRUCTURE HAVING A GATE STACK  
A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and...
US20090166744 Semiconductor device with deep trench structure  
Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage. The...
US20120319185 NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME  
The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed...
US20130316505 CONTROL OF LOCAL ENVIRONMENT FOR POLYSILICON CONDUCTORS IN INTEGRATED CIRCUITS  
A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of...
US20140225065 NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF  
A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded...
US20120184073 PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE  
A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k...
US20130248952 CAPPING DIELECTRIC STRUCTURE FOR TRANSISTOR GATES  
The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description...
US20150155280 IMPLEMENTING BURIED FET BELOW AND BESIDE FINFET ON BULK SUBSTRATE  
A method and circuit for implementing an enhanced transistor topology enabling enhanced current capability with added device drive strength with buried field effect transistors (FETs) below and...
US20120199911 VERTICAL DISCRETE DEVICE WITH DRAIN AND GATE ELECTRODES ON THE SAME SURFACE AND METHOD FOR MAKING THE SAME  
The present technology discloses a vertical discrete device with gate and drain electrodes on the same surface and method for making the same. The vertical discrete device comprises a deep gate...
US20150155385 SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS  
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain...
US20090197382 MULTI-GATED, HIGH-MOBILITY, DENSITY IMPROVED DEVICES  
Disclosed herein are embodiments of an improved method of forming p-type and n-type MUGFETs with high mobility crystalline planes in high-density, chevron-patterned, CMOS devices. Specifically,...
US20150255605 METHOD TO ENHANCE STRAIN IN FULLY ISOLATED FINFET STRUCTURES  
Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions...
US20120115296 TUNNEL FIELD-EFFECT TRANSISTOR WITH GATED TUNNEL BARRIER  
A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the...
US20090101940 DUAL GATE FET STRUCTURES FOR FLEXIBLE GATE ARRAY DESIGN METHODOLOGIES  
A gate array cell adapted for standard cell design methodology or programmable gate array that incorporates a dual gate FET device to offer a range of performance options within the same unit cell...
US20150179786 MOLDED DIELECTRIC NANOSTRUCTURE  
An embodiment concerns selective etching of a structure (e.g., a fin) to form a void with the shape of the original structure. This void then functions as a mold. Flowable dielectric material...
US20110133280 DIFFERENT THICKNESS OXIDE SILICON NANOWIRE FIELD EFFECT TRANSISTORS  
A method (that produces a structure) patterns at least two wires of semiconductor material such that a first wire of the wires has a larger perimeter than a second wire of the wires. The method...
US20140326952 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES  
Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to...
US20090121291 DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD  
Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch...
US20150236130 METHOD FOR FABRICATING FINFET WITH SEPARATED DOUBLE GATES ON BULK SILICON  
Disclosed herein is a method for fabricating a FinFET with separated double gates on a bulk silicon, comprising: forming a pattern for a source, a drain and a thin bar connecting the source and...
US20130181299 Strain Engineering in Three-Dimensional Transistors Based on Strained Isolation Material  
In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the...
US20150076622 REDUCING GATE EXPANSION AFTER SOURCE AND DRAIN IMPLANT IN GATE LAST PROCESS  
A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide...
US20140319614 FINFET CHANNEL STRESS USING TUNGSTEN CONTACTS IN RAISED EPITAXIAL SOURCE AND DRAIN  
Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain,...
US20140133218 Memory Cell  
A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first...
US20150129830 NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS  
A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in...
US20070259485 Electronic device including semiconductor fins and a process for forming the electronic device  
An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and...
US20110312140 MULTIPLE-GATE TRANSISTORS AND PROCESSES OF MAKING SAME  
A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an...
US20080277745 FIN FILLED EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME  
A fin field effect transistor and method of forming the same. The fin field effect transistor comprises a semiconductor substrate having a fin structure and between two trenches with top portions...
US20080150029 MEMORY SYSTEM WITH FIN FET TECHNOLOGY  
A method for manufacturing a memory system is provided including forming a charge-storage layer on a first insulator layer including insulating the charge-storage layer from a vertical fin,...
US20150179756 Metal Gate and Gate Contact Structure for FinFET  
An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate...
US20080157225 SRAM and logic transistors with variable height multi-gate transistor architecture  
Multi-gate transistors having different channel widths formed on non-planar semiconductor bodies have different sidewall heights and method of manufacturing the same. In an embodiment, a...
US20090104745 INTEGRATION METHOD FOR DUAL DOPED POLYSILICON GATE PROFILE AND CD CONTROL  
In accordance with the present teachings, methods of making dual doped polysilicon gates are provided. The method can include providing a semiconductor structure including a plurality of...
US20080142907 ISOLATED MULTIGATE FET CIRCUIT BLOCKS WITH DIFFERENT GROUND POTENTIALS  
An electronic circuit on a semiconductor substrate having isolated multiple gate field effect transistor circuit blocks is disclosed. In some embodiments, an electronic circuit has a substrate...