Applications in Class 438/218

Matches 1 - 50 out of 131

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Match	Document	Document Title
1	US20090014807	DUAL STRESS LINERS FOR INTEGRATED CIRCUITS Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for...
2	US20050205961	Model-based insertion of irregular dummy features A semiconductor device includes an electric circuit, a first conductive feature coupled to the electric circuit, a dielectric material isolating the first conductive feature, and at least two...
3	US20110006372	FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are...
4	US20140315362	CMOS Transistor With Dual High-k Gate Dielectric A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A...
5	US20120178227	REPLACEMENT GATE CMOS A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate...
6	US20130270645	WORKFUNCTION METAL STACKS FOR A FINAL METAL GATE Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate,...
7	US20150179647	CMOS INVERTERS AND FABRICATION METHODS THEREOF A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the...
8	US20080268589	SHALLOW TRENCH DIVOT CONTROL POST The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a...
9	US20130189818	TRENCH ISOLATION AND METHOD OF FABRICATING TRENCH ISOLATION Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the...
10	US20150102416	DUAL-METAL GATE CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type...
11	US20110156144	Compensated Isolated P-WELL DENMOS Devices An integrated circuit with a core PMOS transistor formed in a first n-well and an isolated DENMOS (iso-DENMOS) transistor formed in a second n-well where the depth and doping of the first and...
12	US20120187482	FABRICATION OF CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers...
13	US20090179193	CARBON NANOTUBE BASED INTEGRATED SEMICONDUCTOR CIRCUIT Gate electrodes are formed on a semiconducting carbon nanotube, followed by deposition and patterning of a hole-inducing material layer and an electron inducing material layer on the carbon...
14	US20070072357	Method of manufacturing devices having vertical junction edge Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed...
15	US20100109091	RECESSED DRAIN AND SOURCE AREAS IN COMBINATION WITH ADVANCED SILICIDE FORMATION IN TRANSISTORS During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch...
16	US20120094447	METHOD FOR INTEGRATION OF DUAL METAL GATES AND DUAL HIGH-K DIELECTRICS IN CMOS DEVICES The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or...
17	US20080157224	Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a...
18	US20100237424	REPLACEMENT GATE CMOS A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate...
19	US20050230763	Method of manufacturing a microelectronic device with electrode perturbing sill A method of manufacturing a microelectronic device. The method includes providing a substrate and forming a patterned feature located over the substrate and a plurality of doped regions. The...
20	US20080150037	Selective STI Stress Relaxation Through Ion Implantation A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent...
21	US20140339647	DENSELY PACKED STANDARD CELLS FOR INTEGRATED CIRCUIT PRODUCTS, AND METHODS OF MAKING SAME One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a...
22	US20080261361	Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the...
23	US20150011060	DUAL EPI CMOS INTEGRATION FOR PLANAR SUBSTRATES Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the...
24	US20140138775	DUAL EPI CMOS INTEGRATION FOR PLANAR SUBSTRATES Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the...
25	US20080121985	STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS Disclosed are embodiments of improved MOSFET and CMOS structures that provides for increased control over short channel effects. Also disclosed are embodiments of associated methods of forming...
26	US20070037340	Fabrication method for fabricating a semiconductor structure and semiconductor structure In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active...
27	US20090142892	Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained...
28	US20050255648	Silicon based substrate hafnium oxide top environmental/thermal top barrier layer and method for preparing A top barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment and comprises at least 65...
29	US20090011555	Method of manufacturing CMOS integrated circuit In a method of manufacturing a CMOS integrated circuit according to the present invention, a PSD step (step of forming P-type source/drain regions) is first carried out, and an NSD step (step of...
30	US20130102117	Manufacturing Processes for Field Effect Transistors Having Strain-Induced Chanels One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect...
31	US20110033993	METHOD OF FABRICATING CMOS TRANSISTOR The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is...
32	US20090020821	DUAL WORKFUNCTION SEMICONDUCTOR DEVICE A dual workfunction semiconductor device which comprises a first and second control electrode comprising a metal-semiconductor compound, e.g. a silicide or a germanide, and a dual workfunction...
33	US20090191675	Method for Forming CMOS Transistors Having FUSI Gate Electrodes and Targeted Work Functions A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a...
34	US20090221116	Method for Manufacturing Semiconductor Device Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is...
35	US20080268588	RECESSED GATE CHANNEL WITH LOW Vt CORNER A recessed gate FET device includes a substrate having an upper and lower portions, the lower portion having a reduced concentration of dopant material than the upper portion; a trench-type gate...
36	US20100052057	HIGH VOLTAGE DEVICE WITH REDUCED LEAKAGE A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a...
37	US20080179684	METHOD OF FABRICATING A STRAINED SILICON CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR TRANSISTOR AND STRUCTURE THEREOF The present invention relates to a method of fabricating strained silicon channel complementary metal oxide semiconductor (CMOS) transistor by using an etching process and a planarization process...
38	US20110269277	Reduced STI Topography in High-K Metal Gate Transistors by Using a Mask After Channel Semiconductor Alloy Deposition In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate...
39	US20130161757	CMOS Device for Reducing Charge Sharing Effect and Fabrication Method Thereof The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed...
40	US20080191287	METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a...
41	US20150243663	METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED USING THE SAME A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area...
42	US20100035393	METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING RADIATION HARDENED INSULATORS A method is provided for fabricating a semiconductor device and more particularly to a method of manufacturing a semiconductor device having radiation hardened buried insulators and isolation...
43	US20110076814	METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a...
44	US20080206942	METHOD FOR FABRICATING STRAINED-SILICON METAL-OXIDE SEMICONDUCTOR TRANSISTORS A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on...
45	US20150111351	Method for Manufacturing a Field Effect Transistor of a Non-Planar Type A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation...
46	US20150118807	METHOD OF FABRICATING AN INTEGRATED CIRCUIT DEVICE A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The...
47	US20140349451	COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE HAVING GATE STRUCTURES CONNECTED BY A METAL GATE CONDUCTOR A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active...
48	US20130168776	Complementary Metal Oxide Semiconductor (CMOS) Device Having Gate Structures Connected By A Metal Gate Conductor A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active...
49	US20100197091	GATE DIELECTRIC/ISOLATION STRUCTURE FORMATION IN HIGH/LOW VOLTAGE REGIONS OF SEMICONDUCTOR DEVICE A semiconductor device has a thicker gate dielectric layer (gate-insulation film 16 of, e.g., 40 nm) for a high voltage PMOS transistor (Tr1) that is formed simultaneously in a first thermal...
50	US20100065918	SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME A semiconductor device includes a semiconductor substrate containing a p-type diffusion layer and an n-type diffusion layer which are separated by an element separation film; a gate insulating...

Matches 1 - 50 out of 131

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