Applications in Class 438/197

Matches 1 - 50 out of 869

Match	Document	Document Title
1	US20110186915	REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any...
2	US20140124874	Metal-Gate MOS Transistor and Method of Forming the Transistor with Reduced Gate-to-Source and Gate-to-Drain Overlap Capacitance The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a...
3	US20110266626	GATE DEPLETION DRAIN EXTENDED MOS TRANSISTOR A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and...
4	US20130023093	RECESSED CONTACT FOR MULTI-GATE FET OPTIMIZING SERIES RESISTANCE A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h1); forming...
5	US20120142150	METHOD FOR FORMING METAL GATE AND MOS TRANSISTOR The invention provides a method for forming a metal gate and a method for forming a MOS transistor. The method for forming a metal gate includes: providing a substrate; forming a sacrificial oxide...
6	US20150162445	CHANNEL STRAIN INDUCING ARCHITECTURE AND DOPING TECHNIQUE AT REPLACEMENT POLY GATE (RPG) STAGE The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a...
7	US20080179638	GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging...
8	US20110306170	Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process A method for forming an embedded SiGe (eSiGe) PMOS transistor (102) with improved PMOS poly gate (108) doping concentration without increasing mask count and causing S/D overrun issue. After gate...
9	US20130288435	CET AND GATE CURRENT LEAKAGE REDUCTION IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY HEAT TREATMENT AFTER DIFFUSION LAYER REMOVAL When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after...
10	US20120003798	REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
11	US20090174008	METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING Protecting a FET from plasma damage during FEOL processing by forming a FET-like structure in conjunction with and adjacent to an FET, in a same well as the FET, but having a body doped opposite...
12	US20150050787	FULLY SILICIDED GATE FORMED ACCORDING TO THE GATE-FIRST HKMG APPROACH When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material,...
13	US20150024560	GATE ENCAPSULATION ACHIEVED BY SINGLE-STEP DEPOSITION When forming spacer structures enclosing a gate electrode structure of a transistor, a common problem is given by the thickness variation of the spacer structure obtained as a result of a first...
14	US20150102289	GATE TUNABLE TUNNEL DIODE A gate tunable diode is provided. The gate tunable diode includes a gate dielectric formed on a gate electrode and a graphene electrode formed on the gate dielectric. Also, the gate tunable diode...
15	US20130341704	VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described....
16	US20080048272	SILICIDATION MONITORING PATTERN FOR USE IN SEMICONDUCTOR MANUFACTURING PROCESS A silicidation monitoring pattern may electrically measure resistance of a polygate line after silicidation to measure open and/or short-circuiting of the polygate line. A silicidation monitoring...
17	US20080048271	STRUCTURE AND METHOD TO USE LOW k STRESS LINER TO REDUCE PARASITIC CAPACITANCE A low k stress liner, which replaces conventional stress liners in CMOS devices, is provided. In one embodiment, a compressive, low k stress liner is provided which can improve the hole mobility...
18	US20090321855	Boundaries with elevated deuterium levels A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.
19	US20130032901	FULL SILICIDATION PREVENTION VIA DUAL NICKEL DEPOSITION APPROACH Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a...
20	US20140284725	MOS Transistor Structure and Method of Forming the Structure with Vertically and Horizontally-Elongated Metal Contacts Elongated metal contacts with longitudinal axes that lie in a first direction are formed to make electrical connections to elongated source and drain regions with longitudinal axes that lie in the...
21	US20050077553	Methods of forming multi fin FETs using sacrificial fins and devices so formed Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the...
22	US20090236670	Semiconductor Device and a Manufacturing Process Thereof A semiconductor device has a plurality of drain metal blocks, a plurality of source metal blocks, a plurality of polysilicon strips, a first source metal strip, a first drain metal strip, and a...
23	US20120098075	INTEGRATED ELECTRONIC DEVICE FOR DETECTING MOLECULES AND METHOD OF MANUFACTURE THEREOF An integrated electronic device for detecting gases or biological molecules having a microchip comprising integrated electronics manufactured by the CMOS process. The microchip includes a...
24	US20150097193	ROOM TEMPERATURE TUNNELING SWITCHES AND METHODS OF MAKING AND USING THE SAME The tunneling channel of a field effect transistor comprising a plurality of tunneling elements contacting a channel substrate. Applying a source-drain voltage of greater than a turn-on voltage...
25	US20070004116	Trenched MOSFET termination with tungsten plug structures A metal oxide semiconductor field effect transistor (MOSFET) device includes a termination area. The termination area has a trenched gate runner electrically connected to a trenched gate of said...
26	US20140327047	FET DIELECTRIC RELIABILITY ENHANCEMENT A semiconductor device may be formed by forming a silicon-containing gate dielectric layer over a semiconductor layer. A gate metal layer is formed over the gate dielectric layer; the gate metal...
27	US20130295734	METHOD FOR FORMING GATE, SOURCE, AND DRAIN CONTACTS ON A MOS TRANSISTOR A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at...
28	US20140099764	GRAPHENE DEVICE INCLUDING A PVA LAYER OR FORMED USING A PVA LAYER An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a...
29	US20090309162	SEMICONDUCTOR DEVICE HAVING DIFFERENT FIN WIDTHS A semiconductor device includes at least one source region and at least one drain region. A plurality of fins extend between a source region and a drain region, wherein at least one fin has a...
30	US20070196988	Poly pre-doping anneals for improved gate profiles A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94)...
31	US20130193516	SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION SRAM ICs and methods for their fabrication are provided. One method includes forming dummy gate electrodes overlying a semiconductor substrate and defining locations of gate electrodes for two...
32	US20150145054	TRANSISTOR AND METHOD FOR FORMING THE SAME Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate is provided, having a dummy gate structure including a dummy gate dielectric layer on...
33	US20110097858	Transition metal alloys for use as a gate electrode and devices incorporating these alloys Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or...
34	US20090042346	Electrolyte pattern and method for manufacturing an electrolyte pattern A method for manufacturing a gel electrolyte pattern is disclosed, the method comprising depositing an electrolyte precursor by inkjet printing onto a gelling agent layer. A gel electrolyte...
35	US20150137194	INVERTED CONTACT AND METHODS OF FABRICATION An inverted contact and methods of fabrication are provided. A sacrificial layer is patterned in an inverted trapezoid shape, and oxide is deposited around the pattern. The sacrificial layer is...
36	US20080261358	Manufacture of Lateral Semiconductor Devices A method of manufacturing a lateral semiconductor device comprising a semiconductor body (2) having top and bottom major surfaces (2a, 2b), the body including a drain drift region (6a) of a first...
37	US20150111350	ANISOTROPIC DIELECTRIC MATERIAL GATE SPACER FOR A FIELD EFFECT TRANSISTOR Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally...
38	US20140252412	Strained and Uniform Doping Technique for FINFETs The present disclosure relates to a device and method of forming enhanced channel carrier mobility within a transistor. Silicon carbon phosphorus (SiCP) source and drain regions are formed within...
39	US20140021445	GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide,...
40	US20120256167	GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide,...
41	US20120056249	INTERLAYER FOR ELECTRONIC DEVICES Embodiments in accordance with the present invention provide for the use of polycycloolefins in electronic devices and more specifically to the use of such polycycloolefins as interlayers applied...
42	US20070224748	SEMICONDUCTOR BODY COMPRISING A TRANSISTOR STRUCTURE AND METHOD FOR PRODUCING A TRANSISTOR STRUCTURE A semiconductor body includes a substrate, a buried zone having a first conductivity type that is formed in the substrate, a first zone having the first conductivity type that is above the buried...
43	US20140027862	RF CMOS TRANSISTOR DESIGN An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source...
44	US20110241126	RF CMOS TRANSISTOR DESIGN An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source...
45	US20130277764	Etch Stop Layer Formation In Metal Gate Process A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on...
46	US20140145243	GROUP III-NITRIDE-BASED TRANSISTOR WITH GATE DIELECTRIC INCLUDING A FLUORIDE - OR CHLORIDE- BASED COMPOUND Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer...
47	US20050250272	Biosensor performance enhancement features and designs Isolation of semiconductor based biosensors is described. The present invention is directed to prevention of undesirable influences including, but not limited to, chip leakage current. Several...
48	US20130193494	TRANSISTOR WITH COUNTER-ELECTRODE CONNECTION AMALGAMATED WITH THE SOURCE/DRAIN CONTACT The field effect device includes an active area made from semi-conducting material and a gate electrode separated from the active area by a dielectric gate material. A counter-electrode is...
49	US20110210403	NOVEL STRUCTURES AND METHODS TO STOP CONTACT METAL FROM EXTRUDING INTO REPLACEMENT GATES The methods and structures described are used to prevent protrusion of contact metal (such as W) horizontally into gate stacks of neighboring devices to affect the work functions of these...
50	US20150187957	TRANSISTOR WITH IMPROVED RADIATION HARDNESS An integrated circuit and method with a radiation hard transistor where the gate of the radiation hard transistor does not cross the boundary between active and isolation.

Matches 1 - 50 out of 869

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