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US20090315044 ELECTRO-OPTIC DISPLAYS, AND COMPONENTS FOR USE THEREIN  
An electro-optic display comprises a substrate (100), non-linear devices (102) disposed substantially in one plane on the substrate (100), pixel electrodes (106) connected to the non-linear...
US20060197124 Double gate strained-semiconductor-on-insulator device structures  
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
US20050042810 Semiconductor processing methods of forming integrated circuitry  
Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry...
US20060197123 Methods for forming strained-semiconductor-on-insulator bipolar device structures  
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
US20050003574 Method of creating a high performance organic semiconductor device  
A high temperature thermal annealing process creates a low resistance contact between a metal material and an organic material of an organic semiconductor device, which improves the efficiency of...
US20070257315 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors  
This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for...
US20060008963 Method for forming polysilicon local interconnects  
Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate...
US20060197125 Methods for forming double gate strained-semiconductor-on-insulator device structures  
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
US20120003798 REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN  
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US20070090451 LATERAL DMOS TRANSISTORS INCLUDING RETROGRADE REGIONS THEREIN AND METHODS OF FABRICATING THE SAME  
A metal-oxide semiconductor transistor includes a semiconductor substrate including a source region and a drain region adjacent a surface of the substrate and a drift region between the source...
US20060205132 Scalable integrated logic and non-volatile memory  
A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is...
US20060094193 Semiconductor device including semiconductor regions having differently strained channel regions and a method of manufacturing the same  
By locally modifying the intrinsic stress of a dielectric layer laterally enclosing gate electrode structures of a transistor configuration formed in accordance with in-laid gate techniques, the...
US20120091522 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain...
US20050106798 Semiconductor device and method for fabricating the same  
Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which...
US20130082336 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
An AlGaN/GaN HEMT includes a compound semiconductor multilayer structure, an insertion metal layer in contact with a surface of the compound semiconductor multilayer structure, a gate insulating...
US20100025744 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME  
A semiconductor device includes a gate electrode over a semiconductor substrate, a channel region provided in the semiconductor substrate below the gate electrode, and a strain generation layer...
US20070072354 Structures with planar strained layers  
A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or...
US20140264488 METHODS OF FORMING LOW DEFECT REPLACEMENT FINS FOR A FINFET SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES  
One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned...
US20110097858 Transition metal alloys for use as a gate electrode and devices incorporating these alloys  
Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or...
US20100270535 ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS  
A method for making an electronic device may include forming a selectively polable superlattice comprising a plurality of stacked groups of layers. Each group of layers of the selectively polable...
US20100038628 CHEMICAL DOPING OF NANO-COMPONENTS  
A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided...
US20100035392 SEMICONDUCTOR DEVICE  
A semiconductor device includes a semiconductor substrate having a semiconductor layer, a gate electrode, a source region, a drain region, an element separation insulating film layer and a wiring....
US20050077553 Methods of forming multi fin FETs using sacrificial fins and devices so formed  
Methods of forming multi fin Field Effect Transistors (FET) can include forming a first fin having opposing sidewalls protruding from a substrate and epitaxially growing second fins on the...
US20090305474 STRAINED-SILICON CMOS DEVICE AND METHOD  
The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain...
US20070262363 Low temperature fabrication of discrete silicon-containing substrates and devices  
Fabrication methods and processes are described, the methods and processes occurring at a low-temperature and involving passivation. The methods and processes easily incorporate annealing,...
US20060205131 Method for fabricating semiconductor device  
An underlying insulting film of silicon oxide, a gate insulating film of hafnium oxide, a gate electrode of polysilicon, and side walls of silicon oxide are formed above an element formation...
US20060197126 Methods for forming structures including strained-semiconductor-on-insulator devices  
The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
US20090253234 METHODS OF FABRICATING LATERAL DMOS TRANSISTORS INCLUDING RETROGRADE REGIONS THEREIN  
A metal-oxide semiconductor transistor includes a semiconductor substrate including a source region and a drain region adjacent a surface of the substrate and a drift region between the source...
US20080242013 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME  
A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of...
US20060151808 MOSFET device with localized stressor  
MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor...
US20070298558 METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
A semiconductor device includes a first semiconductor region of first type conductivity with a channel region being formed therein, a gate electrode insulatively formed above the channel region, a...
US20050242340 Strained silicon NMOS devices with embedded source/drain  
A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer...
US20120032240 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on...
US20120009744 SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as...
US20070275495 Method for fabricating a pressure sensor using SOI wafers  
A pressure sensor is manufactured by joining two wafers (1a, 14), the first wafer comprising CMOS circuitry and the second being an SOI wafer. A recess is formed in the top material layer of the...
US20060030093 Strained semiconductor devices and method for forming at least a portion thereof  
A method for forming at least a portion of a semiconductor device includes providing a substrate and epitaxially forming an etch stop layer over the substrate. A first layer is provided over the...
US20050156208 Device having multiple silicide types and a method for its fabrication  
Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and...
US20050023623 Gate structure and method  
A MOSFET structure with high-k gate dielectrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material deposition and gate formation.
US20140001576 LOWERING TUNGSTEN RESISTIVITY BY REPLACING TITANIUM NITRIDE WITH TITANIUM SILICON NITRIDE  
Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the...
US20070272967 Method for Modulating the Effective Work Function  
A new MOSFET device is described comprising a metal gate electrode, a gate dielectric and an interfacial layer. The electrostatic potential at an interface between the gate electrode and the gate...
US20070238236 Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain  
A method and apparatus to improve the contact formation of salicide and reduce the external resistance of a transistor is disclosed. A gate electrode is formed on a surface of a substrate. A...
US20050205894 Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network  
In a standard cell, dummy transistors have p-type and n-type dummy gate electrodes. The dummy transistors are in an OFF state all the time. The gate length of each of the dummy gate electrodes is...
US20140264632 SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF  
A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a...
US20130001700 LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE  
A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the...
US20100109044 Optimized Compressive SiGe Channel PMOS Transistor with Engineered Ge Profile and Optimized Silicon Cap Layer  
A semiconductor process and apparatus includes forming PMOS transistors (72) with enhanced hole mobility in the channel region by epitaxially growing a bi-axially stressed forward graded silicon...
US20080286916 METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE  
Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor...
US20060172480 Single metal gate CMOS device design  
A semiconductor device includes a PMOS transistor formed on a substrate structure. The PMOS transistor includes a source and a drain each including a diffusion region in the substrate structure, a...
US20050214996 Method of manufacturing a nonvolatile semiconductor memory device  
Nonvolatile semiconductor memory devices and methods for manufacturing thereof, which provide inhibiting the shortcutting of the channel due to the creation of the bird's beak to promote the...
US20050202615 Nano-enabled memory devices and anisotropic charge carrying arrays  
Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate,...
US20050064639 Method of fabricating SiC semiconductor device  
In a method of fabricating a SiC semiconductor device, a surface of a SiC layer (5, 48, 102) is processed into a cleaned surface terminated at Si. An oxide film (7, 49, 105) is formed on the...

Matches 1 - 50 out of 329 1 2 3 4 5 6 7 >