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US20150170983 PROBE PAD DESIGN TO REDUCE SAW DEFECTS  
An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad...
US20090152544 DISGUISING TEST PADS IN A SEMICONDUCTOR PACKAGE  
A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical...
US20120119778 POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES  
A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the...
US20150041809 VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION  
A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second...
US20140145191 VOLTAGE CONTRAST INSPECTION OF DEEP TRENCH ISOLATION  
A method including forming a first test structure and a second test structure in electrical contact with an inner buried plate and an outer buried plate, respectively, where the first and second...
US20140225110 Default Trim Code Technique  
In a semiconductor chip for an electronic device, a programmable trim code is independent from a default trim code. An output trim code is produced by selecting either the default trim code or the...
US20130130415 METHODS OF TESTING INTEGRATED CIRCUIT DEVICES USING FUSE ELEMENTS  
Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a...
US20100308329 LITHOGRAPHY ROBUSTNESS MONITOR  
The present invention relates to a method and device for monitoring a lithographic process of an integrated circuit. In a first step a design for an integrated circuit is provided. The integrated...
US20150140698 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS  
A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro...
US20150140697 TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS  
A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro...
US20140361298 LITHOGRAPHY PROCESS MONITORING OF LOCAL INTERCONNECT CONTINUITY  
Disclosed is a novel system and method to form local interconnects in a continuity test structure. The method begins with a first set of transistor gate lines and a second set of transistor gate...
US20090321734 CAPACITOR-BASED METHOD FOR DETERMINING AND CHARACTERIZING SCRIBE SEAL INTEGRITY AND INTEGRITY LOSS  
One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe...
US20140206114 CONTACT RESISTANCE TEST STRUCTURE AND METHOD SUITABLE FOR THREE-DIMENSIONAL INTEGRATED CIRCUITS  
A contact resistance test structure, a method for fabricating the contact resistance test structure and a method for measuring a contact resistance while using the contact resistance test...
US20150123129 WAFER LEVEL PACKAGING TECHNIQUES  
In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS...
US20080286888 TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS  
Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at...
US20060157702 Kerf with improved fill routine  
A semiconductor disk which exhibits chip areas arranged next to one another and separated from one another by a kerf. The chip areas in each case exhibit a multiplicity of similar device patterns,...
US20140027772 Wafers and Chips Comprising Test Structures  
Wafers with chips thereon and corresponding chips are provided where test structures or parts thereof are provided in a peripheral chip area of the chip. Corresponding methods are also disclosed.
US20130299850 ACTIVE MATRIX SUBSTRATE, DISPLAY DEVICE, METHOD FOR INSPECTING THE ACTIVE MATRIX SUBSTRATE, AND METHOD FOR INSPECTING THE DISPLAY DEVICE  
An active matrix substrate (2) is provided with first connecting wirings (641, 643, 645, 647) connected to gate terminals (51) to which extraction wirings (611, 613, 615, 617) are connected,...
US20080038849 Evaluation method of fine pattern, manufacturing method of device having the fine pattern  
An evaluation method includes the steps of forming a dummy pattern having a patterned part with the same critical dimension as a minimum critical dimension of an actual device having a fine...
US20150262895 Pillar Structure having Cavities  
An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between...
US20140151698 Test Structures for Post-Passivation Interconnect  
An integrated circuit structure includes a passivation layer, a polymer layer over the passivation layer, and a PPI monitor structure. The PPI monitor structure includes a portion overlying a...
US20140332973 INLINE MEASUREMENT OF THROUGH-SILICON VIA DEPTH  
A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV...
US20080185581 Silicon-on-insulator ("SOI") transistor test structure for measuring body-effect  
According to one exemplary embodiment, a silicon-on-insulator (SOI) transistor test structure includes a gate situated over a semiconductor body and a doped halo under the gate. The SOI transistor...
US20140332812 WAFER AND SYSTEM AND METHOD FOR TESTING THE WAFER  
A wafer is provided. The wafer includes at least one field. The field includes at least one chip, and at least one test chip that generates power using a wireless signal, that provides power to...
US20100032670 ELECTRICAL TEST STRUCTURE TO DETECT STRESS INDUCED DEFECTS USING DIODES  
A serpentine double gated diode array for monitoring stress induced defects is disclosed. The diode array is configured with adjacent gate segments and gate loops in close proximity to active...
US20080217613 POSITIONAL OFFSET MEASUREMENT PATTERN UNIT FEATURING VIA-PLUG AND INTERCONNECTIONS, AND METHOD USING SUCH POSITIONAL OFFSET MEASUREMENT PATTERN UNIT  
In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be...
US20090162954 AC Impedance Spectroscopy Testing of Electrical Parametric Structures  
Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A...
US20120250429 SECURITY-PROTECTION OF A WAFER OF ELECTRONIC CIRCUITS  
A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing...
US20090166618 TEST STRUCTURE FOR MONITORING PROCESS CHARACTERISTICS FOR FORMING EMBEDDED SEMICONDUCTOR ALLOYS IN DRAIN/SOURCE REGIONS  
By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced...
US20130196458 METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC)  
In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and...
US20140367684 METHODS FOR TESTING INTEGRATED CIRCUITS OF WAFER AND TESTING STRUCTURES FOR INTEGRATED CIRCUITS  
Aspects of the present invention relate to methods of testing an integrated circuit of a wafer and testing structures for integrated circuits. The methods include depositing a sacrificial material...
US20130168673 Intra Die Variation Monitor Using Through-Silicon Via  
An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of...
US20090068772 ACROSS RETICLE VARIATION MODELING AND RELATED RETICLE  
Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying...
US20090083592 SEMICONDCUTOR DEVICE, MEMORY SYSTEM AND CONTROL METHOD OF THE SEMICONDUCTOR DEVICE  
A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a...
US20070267632 Apparatus and Method for Test Structure Inspection  
Herein are described layouts of test structures and scanning methodologies that allow large probe currents to be used so as to allow the detection of resistive defects with a resistance lower than...
US20090058456 MANUFACTURING SYSTEM, MANUFACTURING METHOD, MANAGING APPARATUS, MANAGING METHOD AND COMPUTER READABLE MEDIUM  
There is provided a manufacturing system for manufacturing an electronic device through a plurality of manufacturing stages. The manufacturing system includes a plurality of manufacturing...
US20150155213 Chip Detecting System and Detecting Method  
A chip detecting system is disclosed. The system includes a ball grid array (BGA) chip and a circuit board, the BGA chip includes at least two functional pins being located at a corner of the BGA...
US20070278484 METHOD AND TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS CAUSED BY POROUS BARRIER MATERIALS  
By providing a test structure for electromigration tests in semiconductor devices, which may indicate the status of a barrier layer at the bottom of a test via in the structure, a significantly...
US20140329345 MANUFACTURING METHOD OF ORGANIC LIGHT EMITTING DIODE DISPLAY  
A manufacturing method of an organic light emitting diode (OLED) display includes manufacturing a mother substrate including a plurality of panels formed with a plurality of anodes for each pixel...
US20110272693 MANUFACTURING METHOD OF ULTRASONIC PROBE AND ULTRASONIC PROBE  
The manufacturing yield of semiconductor devices (CMUTs) is improved. Before a polyimide film serving as a protective film is formed, a membrane is repeatedly vibrated to evaluate the breakdown...
US20080145958 MONITORING OF ELECTROSTATIC DISCHARGE (ESD) EVENTS DURING SEMICONDUCTOR MANUFACTURE USING ESD SENSITIVE RESISTORS  
A monitor semiconductor chip that incorporates ESD sensitive resistors is subjected to the same steps in a semiconductor manufacturing process to which functional semiconductor chips are...
US20080067619 Stress sensor for in-situ measurement of package-induced stress in semiconductor devices  
A stress sensor is disclosed herein. The stress sensor includes a plurality of carbon nanotubes in a substrate, and first and second contacts electrically connectable with the plurality of carbon...
US20100297793 IN LINE TEST CIRCUIT AND METHOD FOR DETERMINING INTERCONNNECT ELECTRICAL PROPERTIES AND INTEGRATED CIRCUIT INCORPORATING THE SAME  
A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating...
US20140264335 PACKAGE SUBSTRATE AND METHOD FOR TESTING THE SAME  
A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads...
US20080169466 Test Cells for semiconductor yield improvement  
A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially...
US20100276690 Silicon Wafer Having Testing Pad(s) and Method for Testing The Same  
The present invention relates to a silicon wafer having testing pad(s) and a method for testing the same. The silicon wafer includes a silicon substrate, an insulation layer, at least one testing...
US20090160470 SEMICONDUCTOR AND METHOD  
A semiconductor and method is disclosed. One embodiment includes a detector arrangement to detect the position of a connection element. A probe tip, the detector arrangement including first...
US20120018723 STRUCTURE AND METHOD FOR TESTING THROUGH-SILICON VIA (TSV)  
A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a...
US20150187655 METHOD TO IMPROVE TRANSISTOR MATCHING  
A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust...
US20140065738 LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS  
A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts,...

Matches 1 - 50 out of 194 1 2 3 4 >