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US20120083076 Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same  
A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and...
US20140339639 MULTI-DIRECTION WIRING FOR REPLACEMENT GATE LINES  
A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of...
US20110241116 FET with FUSI Gate and Reduced Source/Drain Contact Resistance  
A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully...
US20140051213 Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices  
A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are...
US20110127493 SELF ALIGNED CARBIDE SOURCE/DRAIN FET  
A field effect transistor includes a metal carbide source portion, a metal carbide drain portion, an insulating carbon portion separating the metal carbide source portion from the metal carbide...
US20130260516 Asymmetric FET Formed Through Use of Variable Pitch Gate for Use as Logic Device and Test Structure  
Asymmetric FET devices and methods for fabrication thereof that employ a variable pitch gate are provided. In one aspect, a method for fabricating a FET device includes the following steps. A...
US20120190155 NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN  
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire...
US20120181549 STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS  
A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate;...
US20110248343 Schottky FET With All Metal Gate  
A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer;...
US20120007051 Process for Forming a Surrounding Gate for a Nanowire Using a Sacrificial Patternable Dielectric  
Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is...
US20110315950 NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE  
In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include...
US20120056161 GRAPHENE TRANSISTOR WITH A SELF-ALIGNED GATE  
A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited...
US20110114919 SELF-ALIGNED GRAPHENE TRANSISTOR  
A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating...
US20110133163 NANOWIRE FET HAVING INDUCED RADIAL STRAIN  
An intermediate process device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads, a gate including a gate conductor surrounding the nanowire and...
US20110133166 NANOWIRE FET HAVING INDUCED RADIAL STRAIN  
A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided...
US20090311835 NANOWIRE MOSFET WITH DOPED EPITAXIAL CONTACTS FOR SOURCE AND DRAIN  
A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire...
US20140295626 ETCHANT COMPOSITION, AND METHOD OF MANUFACTURING A DISPLAY SUBSTRATE USING THE SAME  
An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent...
US20110309332 EPITAXIAL SOURCE/DRAIN CONTACTS SELF-ALIGNED TO GATES FOR DEPOSITED FET CHANNELS  
A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric...
US20130105909 HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE  
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include...
US20110233522 p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors  
Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET...
US20140017856 On-SOI integrated circuit comprising a subjacent protection transistor  
An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer...
US20120009740 METHOD FOR FABRICATING SOI HIGH VOLTAGE POWER CHIP WITH TRENCHES  
A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the...
US20130143370 Logic Switch and Circuits Utilizing the Switch  
A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage...
US20090227075 ETCHANT COMPOSITION, PATTERNING CONDUCTIVE LAYER AND MANUFACTURING FLAT PANEL, DISPLAY DEVICE USING THE SAME  
An etchant composition that allows simplification and optimization of semiconductor manufacturing process is presented, along with a method of patterning a conductive layer using the etchant and a...
US20130175503 Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process  
A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A...
US20060148139 Selective second gate oxide growth  
The invention comprises a method of dual oxide gate formation comprising the steps of forming a first gate oxide and forming a second gate oxide using in-situ steam generation oxidation.
US20120104470 REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN  
A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable...
US20100330751 Single Electron Transistor Operating at Room Temperature and Manufacturing Method for Same  
The present invention relates to a single-electron transistor (SET) operating at room temperature and a method of manufacturing the same, and to be specific, to a single-electron transistor...
US20100065820 Nanotube Device Having Nanotubes with Multiple Characteristics  
A carbon nanotube of a nanotube device has at least two segments with different characteristics. The segments meet at a junction and a diameter of the carbon nanotube on either side of the...
US20150056758 GRAPHENE ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME  
The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide,...
US20090166738 RAM CELL INCLUDING A TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE EXTENSIONS  
In a floating body storage transistor, the dopant concentration at the emitter side of the parasitic bipolar transistor may be significantly increased on the basis of a tilted implantation...
US20140363933 COPPER-ALLOY BARRIER LAYERS FOR METALLIZATION IN THIN-FILM TRANSISTORS AND FLAT PANEL DISPLAYS  
In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an...
US20110183476 ETCHING SOLUTION COMPOSITION AND METHOD OF ETCHING USING THE SAME  
An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH4+)-containing compound, a cyclic amine compound, and the...
US20110017989 PIXEL STRUCTURE, ORGANIC ELECTRO-LUMINESCENCE DISPLAY UNIT, AND FABRICATING METHOD THEREOF  
A pixel structure is disposed on a substrate and includes a gate, a gate insulating layer, a patterned metal-oxide layer, an etching stop layer, a source, and a drain. The gate is disposed on the...
US20110241073 STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN  
A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially...
US20120138886 SILICON AND SILICON GERMANIUM NANOWIRE STRUCTURES  
Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to...
US20110253980 Source/Drain Technology for the Carbon Nano-tube/Graphene CMOS with a Single Self-Aligned Metal Silicide Process  
Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a...
US20120261644 STRUCTURE AND METHOD OF MAKING GRAPHENE NANORIBBONS  
Disclosed is a ribbon of graphene less than 3 nm wide, more preferably less than 1 nm wide. In a more preferred embodiment, there are multiple ribbons of graphene each with a width of one of the...
US20150108479 THIN-FILM TRANSISTORS INCORPORATED INTO THREE DIMENSIONAL MEMS STRUCTURES  
This disclosure provides systems, methods and apparatus for forming electromechanical systems (EMS) displays where the area of a substrate occupied by a pixel circuit can be reduced if portions of...
US20080303063 Capacitorless DRAM and methods of manufacturing the same  
Provided are a capacitorless DRAM and methods of manufacturing the same. The capacitorless DRAM may include a substrate including a source, a drain and a channel, a gate on the channel of the...
US20120018809 MOS DEVICE FOR ELIMINATING FLOATING BODY EFFECTS AND SELF-HEATING EFFECTS  
A MOS device having low floating charge and low self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective...
US20140322871 PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT  
Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device...
US20070184586 THIN FILM TRANSISTOR PANEL AND METHOD OF MANUFACTURING THE SAME  
A thin film transistor panel and a method of manufacturing the same are disclosed. The thin film transistor panel includes a thin film transistor including a drain electrode with an opening, and a...
US20080296665 MASK FOR MANUFACTURING TFT, TFT, AND MANUFACTURING THEREOF  
A mask comprises a channel region half-exposure mask structure, a drain mask structure, and a source mask structure, wherein the channel region half-exposure mask structure comprises a channel...
US20090026545 INTEGRATED CIRCUIT EMPLOYING VARIABLE THICKNESS FILM  
An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a...
US20110127492 Field Effect Transistor Having Nanostructure Channel  
A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate...
US20150214496 CNT Thin Film Transistor With High K Polymeric Dielectric  
A thin film transistor (TFT) has a gate electrode; a gate insulation layer, a semiconducting channel separated from the gate electrode by the gate insulation layer; a source electrode and a drain...
US20150004758 ETCHANT, METHOD OF MANUFACTURING METAL WIRING AND THIN FILM TRANSISTOR SUBSTRATE USING THE ETCHANT  
An etchant composition includes about 0.5 weight % to about 20 weight % of persulfate, about 0.01 weight % to about 2 weight % of a fluoride compound, about 1 weight % to about 10 weight % of an...
US20140167164 DEVICE STRUCTURE WITH INCREASED CONTACT AREA AND REDUCED GATE CAPACITANCE  
A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain...
US20150205152 LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF  
The inventive concept relates to a liquid crystal display and a manufacturing method thereof. More particularly, the inventive concept relates to a liquid crystal display including one substrate...