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US20110049576 Homogenous Cell Array  
A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array,...
US20110177658 Standard Cell Architecture and Methods with Variable Design Rules  
Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a...
US20140353727 I/O CELL ESD SYSTEM  
An integrated circuit including an ESD network including a portion located in ESD subareas of a plurality of I/O cells where the ESD subareas are arranged in a row traversing the plurality of I/O...
US20140167815 AREA RECONFIGURABLE CELLS OF A STANDARD CELL LIBRARY  
An integrated circuit using area reconfigurable cells of a standard cell library includes standard cells placed adjacent with one another in rows and columns. Each of the standard cells has a...
US20140327050 STANDARD CELL HAVING CELL HEIGHT BEING NON-INTEGRAL MULTIPLE OF NOMINAL MINIMUM PITCH  
An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal...
US20110298010 Cell Library, Integrated Circuit, and Methods of Making Same  
A cell library intended to be used to form an integrated circuit, this library defining a first cell including a first MOS transistor of minimum dimensions, and a second cell including a second...
US20120223368 Power Routing in Standard Cells  
An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage....
US20140252419 MEMS DEVICE AND METHOD OF MANUFACTURE  
A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels,...
US20110076810 Three Dimensional Multilayer Circuit  
A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template...
US20100159648 ELECTROPHOTOGRAPH PRINTED ELECTRONIC CIRCUIT BOARDS  
The present invention provides a device for producing printed electronic circuits using electrophotography
US20060141678 Forming a nanotube switch and structures formed thereby  
Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising a power pad, and attaching a nanotube comprising at least one...
US20110240952 PROGRAMMABLE CROSSPOINT DEVICE WITH AN INTEGRAL DIODE  
A programmable crosspoint device with an integral diode includes a first crossbar, a second crossbar, a metallic interlayer, and a switching oxide layer interposed between the first crossbar and...
US20140225165 INTERCONNECT WIRING SWITCHES AND INTEGRATED CIRCUITS INCLUDING THE SAME  
An electronic circuit, includes a plurality of electronic devices configured as interconnected to provide one or more circuit functions and at least one interconnect structure that includes a...
US20110042832 EXTENDABLE CONNECTOR AND NETWORK  
Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled...
US20090155962 Method for fabricating pitch-doubling pillar structures  
A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming...
US20080218919 PROTECTION OF INTEGRATED ELECTRONIC CIRCUITS FROM ELECTROSTATIC DISCHARGE  
Circuit nodes are identified which, in unpowered mode, can be charged with positive or negative charges but cannot be discharged. Then protective elements are added to allow the discharge of these...
US20110248744 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC  
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
US20110089972 SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC  
A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors...
US20100090263 MEMORY DEVICES INCLUDING SEMICONDUCTOR PILLARS  
One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column...
US20100231256 SPARE CELL LIBRARY DESIGN FOR INTEGRATED CIRCUIT  
A cell based design layout of an application specific integrated circuit (ASIC) having a function has reduceddecreased power leakage because functionally unconnected additional cells or spare...
US20110020986 Offset Geometries for Area Reduction In Memory Arrays  
An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding...
US20110018035 Offset Geometries for Area Reduction in Memory Arrays  
An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding...
US20080218061 PIXEL STRUCTURE OF ORGANIC ELECTROLUMINESCENT DISPLAY PANEL AND METHOD OF MAKING THE SAME  
A pixel structure of an organic electroluminescent display panel has a plurality of sub-pixel regions. Each of the sub-pixel regions has a plurality of organic luminescent devices electrically...
US20110156103 Method and System to Reduce Area of Standard Cells  
A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a...
US20090207654 Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same  
Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality...
US20090224683 Complimentary Application Specific Integrated Circuit for Compact Fluorescent Lamps  
In a lighting ballast there are typically several discrete components that combine to take an external AC signal and convert it to a DC signal, and back to an AC signal for powering a lamp....
US20110317469 NON-VOLATILE SAMPLER  
A non-volatile sampler including a row line for receiving an input signal to be sampled, the row line intersecting a number of column lines, non-volatile storage elements being disposed at...
US20100001267 NRAM ARRAYS WITH NANOTUBE BLOCKS, NANOTUBE TRACES, AND NANOTUBE PLANES AND METHODS OF MAKING SAME  
NRAM arrays with nanotube blocks, traces and planes, and methods of making the same are disclosed. In some embodiments, a nanotube memory array includes a nanotube fabric layer disposed in...
US20090040829 LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES  
A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of...
US20150249091 NVM LAYOUT  
A memory device can include an array of NOR memory cells, each memory cell including a floating gate, a source on a source side of the floating gate, a drain on a drain side of the floating gate,...
US20100163946 SEMICONDCUTOR DEVICE HAVING VERTICAL GATE AND METHOD FOR FABRICATING THE SAME  
A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top...
US20060240602 Transistor for active matrix display and a method for producing said transistor  
A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction...
US20100297815 Transistor Layout for Manufacturing Process Control  
A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first...
US20070240092 Methods of Fabricating Application Specific Integrated Circuit (ASIC) Devices that Include Both Pre-Existing and New Integrated Circuit Functionality and Related ASIC Devices  
A method of fabricating a semiconductor integrated circuit, such as an ASIC, and a semiconductor integrated circuit using the same, are cost effective and allow lower non-recurring engineering...
US20140264461 METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS  
Methods for forming a DSA pre-patterned semiconductor transistor layout and the resulting devices are disclosed. Embodiments may include forming a pre-patterned transistor layout by directed...
US20100140665 Gallium Nitride Material Devices and Thermal Designs Thereof  
Gallium nitride material devices and methods associated with the devices are described. The devices may be designed to provide enhanced thermal conduction and reduced thermal resistance. The...
US20110165737 Method for designing semiconductor integrated circuit which includes metallic wiring connected to gate electrode and satisfies antenna criterion  
A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of...
US20100164543 LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE SAME  
In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS...
US20060091423 Layer fill for homogenous technology processing  
Spare transistors are formed in regions of a semiconductor device where functional transistors are not formed, providing uniformity in etch and polishing processes, and resulting in transistors...
US20050145923 NAND flash memory with enhanced program and erase performance, and fabrication process  
NAND flash memory cell array and fabrication process in which control gates and floating gates are stacked in pairs arranged in rows between a bit line diffusion and a common source diffusion,...
US20120147675 Nonvolatile Stacked Nand Memory  
A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND...
US20090085069 NAND-type Flash Array with Reduced Inter-cell Coupling Resistance  
In a NAND-type nonvolatile reprogrammable memory array, inter-cell coupling resistance between adjoining memory cells is reducing by forming metal silicide insets embedded in the diffusion zone of...
US20080315326 Method for forming an integrated circuit having an active semiconductor device and integrated circuit  
An integrated circuit having an active semiconductor device is formed comprising a trench defined by conductor lines previously formed.
US20100301305 PHASE CHANGE MEMORY DEVICE WITH ALTERNATING ADJACENT CONDUCTION CONTACTS AND FABRICATION METHOD THEREOF  
A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction...
US20100255642 CCD Array with Integrated High Voltage Protection Circuit  
A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a...
US20150118803 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES  
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations...
US20120256235 LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES  
A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations...
US20080035926 DISPLAY DEVICE AND DISPLAY DEVICE MANUFACTURING METHOD  
An active matrix type display device, wherein a pixel circuit is formed using a plurality of thin film transistors in which thin semiconductor films forming channel regions of the thin film...
US20150248521 Methods and Apparatus for SRAM Cell Structure  
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at...
US20090231943 Multi-Bank Memory Device Method and Apparatus  
In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the...

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