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US20100002143 DISPLAY APPARATUS AND PHASE DETECTION METHOD THEREOF  
A display apparatus including an analog-to-digital converter (ADC) module, a phase detecting module, and a clock generator is provided. The ADC module is used to receive a first analog video...
US20090041167 Demodulator, Receiver, and Demodulation Method  
In an OFDM receiver with a diversity configuration having a plurality of demodulation modules, to perform FFT window position recovery and clock recovery, the gain values calculated by the AGC...
US20060018417 Phase detection circuit and method thereof and clock recovery circuit and method thereof  
The phase detection circuit may allow an operating speed of a semiconductor circuit to be increased irrespective of whether a combinational logic circuit within the semiconductor circuit operates...
US20070230646 PHASE RECOVERY FROM FORWARD CLOCK  
A clock phase recovery circuit in a communications receiver generates a sample clock signal for recovering data from a received data signal. The sample clock signal is based at least in part on...
US20070047687 PHASE DETECTOR AND RELATED PHASE DETECTING METHOD THEREOF  
A phase detector for detecting a phase difference between a first signal and a second signal is disclosed. The phase detector includes: a difference determining module, a phase leading/lagging...
US20060274876 Deriving fractional clock period error information  
Techniques for determining a synchronization error of a local clock by deriving fractional clock period error information enable increased accuracy in local clock synchronization without...
US20090147901 Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device  
A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a...
US20080273648 Means To Reduce The PLL Phase Bump Caused By A Missing Clock Pulse  
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in...
US20070127615 DC technique for eliminating phase ambiguity in clocking signals  
An integrated circuit including: a clock signal distribution network for carrying two global clock signals traveling in opposite directions; a plurality of local clocking regions arranged along...
US20070147570 Phase detector for data communications  
In one embodiment, a phase error signal generated by a phase detector is equalized to compensate for the distortion in the phase error signal due to finite circuit speeds. The equalization may be...
US20050265504 Clock recovery circuit and a method of generating a recovered clock signal  
The present invention relates to a clock recovery circuit for generation of a recovered clock signal from a received data stream using a weighted combination of phase component signals. The clock...
US20080002801 Fast-settling clock generator  
A clock generator with a fast settling time features a coarse-tuning circuit that is executed a single time, and a fine-tuning circuit that is executed periodically. The fine-tuning circuit sends...
US20080049884 LINEAR PHASE DETECTOR AND CLOCK/DATA RECOVERY CIRCUIT THEREOF  
A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have...
US20090207961 PHASE SYNCHRONIZATION CIRCUIT AND RECEIVER HAVING THE SAME  
A phase synchronization circuit includes a controlled oscillator configured to generate a first oscillation signal and a second oscillation signal that have a common frequency but different phase...
US20080112524 Phase locked loops capable of burn-in testing with increased locking range and burn-in testing method thereof  
In phase locked loop, a phase detector detects a phase difference between a first clock signal and a second clock signal and output a first output signal based on the detected difference. A charge...
US20070064850 Data reproduction circuit  
This is a data reproduction circuit for receiving data and reproducing the data and its clock which comprises an over-sampling determination circuit for sampling the received data by a clock with...
US20060083343 Clock generation using phase interpolators  
A serial data link, which derives an incoming data clock linked to the data rate of the incoming data, also generates an outgoing data clock that is used to re-transmit the data from the serial...
US20150055552 CONFIGURABLE RF CARRIER PHASE NOISE SHAPING  
A method and system is includes configurable carrier phase noise shaping. A fractional phase locked loop (PLL) uses a bank of delta-sigma modulators (DSM) to generate fractional ratios of the...
US20140362963 CORRECTING APPARATUS FOR TIMING RECOVERY OF RECEIVER AND METHOD THEREOF  
A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus...
US20100061499 PHASE/FREQUENCY DETECTOR FOR A PHASE-LOCKED LOOP THAT SAMPLES ON BOTH RISING AND FALLING EDGES OF A REFERENCE SIGNAL  
A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock...
US20130251084 LOW JITTER CLOCK RECOVERY CIRCUIT  
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase...
US20070047688 Frequency detecting circuit and method, and semiconductor apparatus including frequency detecting circuit  
A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a...
US20070286321 Linear sample and hold phase detector for clocking circuits  
Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference...
US20140029708 DYNAMIC OPTIMIZATION OF CARRIER RECOVERY PERFORMANCE FOR COMMUNICATION SYSTEMS  
Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that...
US20060050827 Synchronization device and semiconductor device  
An apparatus for performing a channel-to-channel delay correction and frame synchronization with low latency includes, on each of a plurality of channels, a clock-and-data recovery circuit for...
US20090122939 Wide range and dynamically reconfigurable clock data recovery architecture  
Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of...
US20100034333 Methods And Apparatus For Improved Phase Linearity In A Multi-Phase Based Clock/Timing Recovery System  
Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase...
US20090074125 TIME-INTERLEAVED CLOCK-DATA RECOVERY AND METHOD THEREOF  
A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and...
US20070223637 PHASE DETECTOR  
A phase detector is described, comprising a pair of output-latched half-transparent (OLHT) module each receiving two input terminals with an inverse connection relationship with respect to two...
US20090154622 System and Method for Filter Response Switching  
A system and method are provided for efficiently switching a loop bandwidth using stored values in a digital filter of a phase-locked loop system. In a first timeslice, an input signal is...
US20150207648 Modular Low Power Serializer-Deserializer  
Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end...
US20070177702 Receiving data over channels with intersymbol interference  
A method of receiving data includes sampling the data at data sampling points to obtain data samples corresponding to information contained in the data, and sampling the data at intermediate...
US20070206711 Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit  
Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator...
US20060140309 Clock and data recovery circuits  
A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a...
US20060256908 FREQUENCY COMPARATOR UTILIZING ENVELOPING-EVENT DETECTION VIA SYMBOLIC DYNAMICS OF FIXED OR MODULATED WAVEFORMS  
Systems, algorithms, circuits, and methods for pattern detection of signature events in signal dynamics defined by instantaneous states of applied square-wave signals. Selected patterns may be...
US20100310030 PHASE LOCKED LOOP DEVICE AND METHOD THEREOF  
A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector...
US20080107222 System and method for signal phase correction  
A method and apparatus for correcting a phase of a phase-modulated signal for blind demodulation. The method and apparatus generally include the creation of a plurality of angle bins, wherein each...
US20140362962 System and Method For Adaptive N-Phase Clock Generation For An N-Phase Receiver  
An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase...
US20070092049 Soft-decision phase detector for low signal-to-noise (SNR) phase tracking  
A method and apparatus is disclosed for detecting the amount of unknown offset present in a received data stream. The unknown phase offset may offset the phase of the transmitted data stream from...
US20070237277 Method and Integrated Circuit for Controlling an Oscillator Signal  
An integrated circuit is provided. The integrated circuit includes a delay locked loop comprising a binary phase detector which generates a binary phase detector signal, and a decimator receiving...
US20080130816 Serializer deserializer circuits  
A phase lockedcircuit comprising a phase detector for comparing an incoming serial data signal with a feedback clock signal and generating a digital phase detector output signal representing a...
US20100040185 METHODS AND APPARATUS FOR DIGITAL CLOCK RECOVERY  
A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency...
US20140016731 Millimeter-Wave Band Radio Transceiver Device  
Provided is a millimeter wavelength range transceiver device which can improve phase noise characteristics and which can also independently calibrate each respective local oscillator of a...
US20070253512 Method for acquiring timing and carrier synchronization of offset-QPSK modulated signals  
Embodiments of the invention consist in a method of carrier synchronization, comprising determining a frequency offset estimate from a rate of change of a phase difference between a local...
US20050047540 Phase detector and method of detecting phase  
Disclosed is a method for rapidly and precisely detecting phase by a level trigger method. A phase detector includes a false lock preventing section which includes multiple latches, a lock...
US20150188551 CLOCK RECOVERY USING QUANTIZED PHASE ERROR SAMPLES USING JITTER FREQUENCY-DEPENDENT QUANTIZATION THRESHOLDS AND LOOP GAINS  
A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a...
US20080063128 System and method for implementing a phase detector to support a data transmission procedure  
A system and method for effectively supporting a data transmission procedure includes a phase-locked loop with a phase detector that compares a clock signal and input data to generate a phase...
US20150207502 Method and Apparatus for Reference-Less Repeater with Digital Control  
Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency...
US20150188697 MULTIMEDIA INTERFACE RECEIVING CIRCUIT  
A multimedia interface receiving circuit includes a phase-locked loop (PLL) and four signal processing channels. Each of the channels includes a phase detecting circuit. In a High-Definition...
US20140126678 ALL DIGITAL BURST-MODE CLOCK AND DATA RECOVERY (CDR)  
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase...

Matches 1 - 50 out of 68 1 2 >