Matches 1 - 40 out of 40


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US20070201593 Egress pointer smoother  
A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, by measuring the average fill, the 3 bytes...
US20070280396 Method and system for advance high performance bus synchronizer  
Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the...
US20080130814 MULTI-LANE ELASTIC BUFFER CLUSTER FOR CLOCK TOLERANCE COMPENSATION AND DE-SKEW AMONG MULTIPLE RECEIVING LANES  
System and method for data transfer with buffer control. According to an embodiment, the present invention provides a system for synchronized data communication. The system includes a first...
US20070126414 Jitter generation  
The present invention relates to a method for generating jitter in a digital data signal, the digital data signal having a predetermined data pattern being stored in a memory, the method...
US20070165762 NICAM audio signal resampler  
A NICAM audio signal re-sampler may include a non-linear interpolator configured to interpolate in a non-linear manner between sequential digital samples that are based on a stream of demodulated...
US20070263755 Method of transmitting time information with fixed latency  
The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the...
US20100054385 ADAPTIVE ELASTIC BUFFER FOR COMMUNICATIONS  
Circuit and method for an adaptive elastic buffer for receiving data including timing signals. Received data is recovered and stored in the adaptive elastic buffer, and a recovery clock pointer is...
US20080101522 Programmable Local Clock Buffer  
A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data...
US20090296868 Method for Shifting Data Bits Multiple Times Per Clock Cycle  
A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following...
US20050220240 Clock synchroniser and clock and data recovery apparatus and method  
A clock synchroniser, and clock and data recovery apparatus incorporating the clock synchroniser, are described, together with corresponding clock synchronisation methods. The clock synchroniser...
US20080056341 Finding Low Frequency Random and Periodic Jitter in High Speed Digital Signals  
Simultaneously measurements of jitter in a high speed signal expected to exhibit both short and long period jitter are made even when the amount of acquisition memory is fixed and cannot be...
US20050013396 Digital clock recovery circuit employing fixed clock oscillator driving fractional delay line  
A clock recovery scheme for a digital communication receiver has a fixed fractional delay line that is driven by a fixed frequency reference clock source, to provide a plurality of respectively...
US20070183551 Method and circuit for obtaining asynchronous demapping clock  
A method and a circuit for obtaining asynchronous demapping clock. The method includes: obtaining a smoothed clock with even gaps in accordance with data to be demapped and a corresponding clock...
US20080112523 DATA SYNCHRONIZATION APPARATUS  
A data synchronization apparatus is provided. The data synchronization apparatus comprises a first-in first-out buffer (FIFO buffer), a control circuit and a phase-locked loop (PLL). The FIFO...
US20090086874 Apparatus and method of elastic buffer control  
A method, system, and apparatus for synchronizing an asynchronous data transmission between a transmitter and a receiver are presented. For example, an elastic buffer can include a symbol storage...
US20080075219 Rate adaptation  
A method and system for providing single stage pointer and overhead processing is disclosed. In accordance with one embodiment of the invention, data including bytes of each of multiple types of...
US20070086554 Data synchronizer and data synchronizing method  
According to an embodiment of the present invention, a data synchronizer for outputting data with a readout clock frequency sync with input data or receiving data with a read-in clock frequency...
US20070201592 Multi-channel fractional clock data transfer  
Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a signal corresponding to a read pointer of a buffer is generated in response to a...
US20070019771 Communication protocol for networked devices  
A communication protocol in a wireless network of a transceiver and a plurality of devices, in which at least one device is a bidirectional device, and in which one or more other devices can be...
US20150200771 METHODS AND SYSTEMS FOR CLOCK DRIFT COMPENSATION INTERPOLATION  
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The...
US20080240326 HIGH SPEED DIGITAL WAVEFORM IDENTIFICATION USING HIGHER ORDER STATISTICAL SIGNAL PROCESSING  
In some embodiments an apparatus includes a higher order statistical signal processor to process a jittered digital signal, a diagonal line average unit to identify a distinct line in a signal...
US20070291888 System and method for an adaptable timing recovery architecture for critically-timed transport applications  
The present invention provides a timing recovery architecture and circuit for recovering the clock timing from a received signal in critically-timed transport applications. The present invention...
US20070172011 Sampling rate mismatch solution  
Methods and apparatuses for compensating for differences in communication system transmit and receive clock signal frequencies include buffer timing modification and sample addition. In buffer...
US20070165761 Method and system for universal sampling rate conversion  
A sampling rate converter (100) is provided. The system can include a data buffer (102), a processor (104) for processing data in the buffer (10), and a plurality of sampling rate lines for...
US20090232266 SIGNAL PROCESSING DEVICE  
A signal processing device includes a phase shifting unit for supplying a second clock signal having a predetermined phase difference relative to a first clock signal, a head recognition bit...
US20070177701 Receiver and method for synchronizing and aligning serial streams  
A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer...
US20080256300 System and method for dynamically reconfiguring a vertex cache  
A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled...
US20080187085 Method and Apparatus for the Capture of Serial Data Amid Jitter  
Serial data in the presence of jitter is captured by clocking the data into several different shift registers, each driven by a clock of the correct frequency but having different phases. In...
US20070058766 Methods and apparatus for recovering serial data  
A phase alignment device for alignment of phase between a data signal and a clock signal is described. The phase alignment device includes a signal generator generating an enable signal configured...
US20090116602 High speed, wide frequency-range, digital phase mixer and methods of operation  
The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The...
US20070025488 RAM-DAC for transmit preemphasis  
Described are transmitters with RAM-DAC based pre-emphasis filters that can be updated adaptively without interfering with data transmission. The memory within the RAM-DAC is divided into active...
US20070140398 Data receiving device and data receiving method  
A receiving device (50) is provided to allow appropriate clock regeneration even for a VBR TS when a stream including video and audio data, such as an MPEG2 TS, is transmitted or received in real...
US20060126770 Methods and apparatus for providing an asynchronous boundary between internal busses in a multi-processor device  
Methods and apparatus provide for transferring data to and from one or more processors of a multi-processor system over a first bus at a first frequency; transferring data to and from one or more...
US20060062338 Method and apparatus for ensuring high quality audio playback in a wireless or wired digital audio communication system  
A communication system synchronizes data received and recovered from a transmission medium to the data transmitted such the there is neither under-run nor overrun of the data due to differences in...
US20070165763 System and method for transporting unaltered optical data stream  
Embodiments of the invention provide systems, apparatuses, and methods for maintaining proper bit sequence as well as the rate at which the bits occur within the data stream, enabling the...
US20050207480 Noise shaped interpolator and decimator apparatus and method  
Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a...
US20100166132 PLL/DLL DUAL LOOP DATA SYNCHRONIZATION  
A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL)...
US20170019245 RECEPTION APPARATUS AND SYSTEM  
A reception apparatus for receiving data from a transmission apparatus includes a data receiver configured to receive a synchronization packet including clock information generated by the...
US20160226655 ELASTIC GEAR FIRST-IN-FIRST-OUT BUFFER WITH FREQUENCY MONITOR  
An elastic gear First-In-First-Out (FIFO) buffer architecture is disclosed. The proposed elastic gear FIFO buffer uses a frequency monitor unit to control clock frequency compensation. By using an...
US20150131766 APPARATUS AND METHOD FOR FREQUENCY LOCKING  
An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the...

Matches 1 - 40 out of 40