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US20140241025 DRAM CELL DESIGN WITH FOLDED DIGITLINE SENSE AMPLIFIER  
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an...
US20060181912 Low-power solid state storage controller for cell phones and other portable appliances  
A storage controller comprising a first interface to exchange data with an appliance, such as a cell phone; a second interface to exchange data with a host system and receive power from the host...
US20070109833 Daisy chain cascading devices  
A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs...
US20090175062 FEEDBACK STRUCTURE FOR AN SRAM CELL  
Embodiments of the present disclosure provide a feedback structure, a method of constructing a feedback structure and an integrated circuit employing the feedback structure. In one embodiment, the...
US20140185353 MEMORY  
A memory in accordance with an embodiment of the present invention may include a first page buffer, a second page buffer arranged adjacent to the first page buffer in a first direction, a global...
US20130329480 SRAM  
The SRAM memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout...
US20140078804 Mask Design With Optically Isolated Via and Proximity Correction Features  
A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define...
US20120230078 STORAGE CIRCUIT  
A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a...
US20130242633 Apparatus for ROM Cells  
A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the...
US20070291557 STACKED SEMICONDUCTOR DEVICE  
Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural...
US20100020584 High Speed Memory Module  
A memory module may include a circuit board connectable to a system memory bus through a plurality of contacts disposed along one edge of the circuit board, the system memory bus having three...
US20080273366 DESIGN STRUCTURE FOR IMPROVED SRAM DEVICE PERFORMANCE THROUGH DOUBLE GATE TOPOLOGY  
A design structure embodied in a machine readable medium used in a design process includes a static random access memory (SRAM) device having a pair of cross-coupled, complementary metal oxide...
US20060056216 Multi-chip card  
A portable object (1) of the smart card type comprises a main circuit (3, 8, 9, 10) for internal processing and storage of data. The main circuit comprises several integrated circuits (3, 10). The...
US20100008152 SEMICONDUCTOR DEVICE INCLUDING DRIVING TRANSISTORS  
A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one...
US20130039111 CONNECTION AND ADDRESSING OF MULTI-PLANE CROSSPOINT DEVICES  
A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and...
US20140112048 N-BIT ROM CELL  
Among other things, an n-bit ROM cell, such as a twin-bit ROM cell, and techniques for addressing one or more ROM cell portions of the n-bit ROM cell are provided. A twin-bit ROM cell comprises a...
US20070109831 Semiconductor product and method for forming a semiconductor product  
A semiconductor product includes a first semiconductor chip that includes input/output circuitry enabling transfer of data from memory banks of the semiconductor product to an external electronic...
US20120155142 PHASE INTERPOLATORS AND PUSH-PULL BUFFERS  
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the...
US20130088907 TRANSISTOR CIRCUIT LAYOUT STRUCTURE  
A transistor circuit layout structure includes a transistor disposed on a substrate and including a source terminal, a drain terminal and a split gate including an independent first block and an...
US20110199806 UNIVERSAL STRUCTURE FOR MEMORY CELL CHARACTERIZATION  
An integrated circuit includes a structure, where the structure includes a memory base cell, a first port set, a second port set, and a set of other ports, where the memory base cell includes a...
US20120206953 MEMORY EDGE CELL  
A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS...
US20090097297 Memory module having star-type topology and method of fabricating the same  
A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two...
US20080256414 SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHOD OUTPUTTING DATA  
A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental...
US20060039189 Magnetic random access memory with tape read line, fabricating method and circuit thereof  
A magnetic random access memory with tape read line, fabricating method and circuit thereof is provided. The memory is composed of a top write line, a bottom write line which is vertical to the...
US20120044734 BIT LINE SENSE AMPLIFIER LAYOUT ARRAY, LAYOUT METHOD, AND APPARATUS HAVING THE SAME  
A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1−i) bit lines and i...
US20090086522 ADDRESS LINE WIRING STRUCTURE AND PRINTED WIRING BOARD HAVING SAME  
An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address...
US20090091964 Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region  
A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a...
US20080219037 INTEGRATED CIRCUIT, MEMORY DEVICE, METHOD OF OPERATING AN INTEGRATED CIRCUIT, AND METHOD OF DESIGNING AN INTEGRATED CIRCUIT  
An integrated circuit, a memory device, a method of operating an integrated circuit and a method of designing an integrated circuit are provided. An integrated circuit comprises a plurality of...
US20080158956 NON-VOLATILE MEMORY MODULE FOR PREVENTING SYSTEM FAILURE AND SYSTEM INCLUDING THE SAME  
A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch...
US20140194077 Passive Interface for an Electronic Memory Device  
A passive interface for connecting an electronic memory device to an exterior circuit is provided. The passive interface includes a signal connection point, a power connection point and a ground...
US20060250834 Displaying a set of data elements  
A set of elements, such as, for example, a path, a directory list, a playlist, and a listing of information associated with a file or a song, may be truncated so that a partial set may be...
US20080037310 Semiconductor memory device and connection method thereof  
A semiconductor memory device comprising a substrate, a memory electrically connected to the substrate, a first and a second transmission/reception units transmitting a signal supplied by the...
US20130286708 MEMORY EDGE CELL  
A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a...
US20130094273 3D MEMORY AND DECODING TECHNOLOGIES  
A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left...
US20100020583 Stacked memory module and system  
A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and...
US20080273364 MEMORY STRUCTURE WITH EMBEDED MULTI-TYPE MEMORY  
A memory includes a first-type memory; and a second-type memory, formed on the first-type memory, wherein the first-type memory is a nonvolatile memory with a stack of conductor/storage/conductor,...
US20090290403 SEMICONDUCTOR DEVICE  
According to an aspect of the present invention, there is provided a semiconductor device including: first and second blocks that each includes a word line group of first to N-th word lines, the...
US20110267866 EXTENSIBLE THREE DIMENSIONAL CIRCUIT HAVING PARALLEL ARRAY CHANNELS  
An extensible three dimensional circuit having parallel array channels includes an access layer and crossbar array layers overlying the access layer and being electrically connected to the access...
US20070201258 Semiconductor memory device capable of controlling drive ability of output driver  
An example embodiment provides a semiconductor memory device. The semiconductor memory device may include an output driver, a delay circuit and an output driver controlling circuit. The output...
US20060133126 Semiconductor memory device capable of switching from multiplex method to non-multiplex method  
There is provided a semiconductor memory device which adopts a multiplex method in which an address signal and a data signal are input into the same terminal, and which is capable of switching...
US20140133210 VARIABLE RESISTIVE ELEMENT, STORAGE DEVICE AND DRIVING METHOD THEREOF  
An element according to an embodiment can transit between at least two states including a low-resistance state and a high-resistance state. The element comprises a first electrode, a second...
US20090185407 Semiconductor Memory Device Having Transistors of Stacked Structure  
Provided is a semiconductor device having transistors of stacked structure. The semiconductor memory device having transistors includes a memory cell array block which includes a plurality of word...
US20090201712 PRESETABLE RAM  
A programmable volatile memory cell has a reset device in communication with a bit store. The reset device may produce a high or low logic state within a latch loop when activated by an assertive...
US20140003114 COMPACT SOCKET CONNECTION TO CROSS-POINT ARRAY  
An integrated circuit may include lines that traverse a cross-point array, the lines fabricated at a first pitch on a first layer, wherein the first pitch is sub-lithographic, and leads on a...
US20150109844 INTEGRATED CIRCUIT AND OPERATING METHOD FOR THE SAME  
An integrated circuit and an operating method for the same are provided. The integrated circuit comprises a stacked structure and a conductive structure. The stacked structure comprises a...
US20130121055 WORD LINE DRIVER CELL LAYOUT FOR SRAM AND OTHER SEMICONDUCTOR DEVICES  
A word line driver cell suitable for RAM devices such as SRAM, static random access memory devices, is provided. The word line driver cell is compatible with double pattern processing techniques...
US20090251940 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE USING A VARIABLE RESISTANCE FILM AND METHOD OF MANUFACTURING THE SAME  
A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode...
US20090196086 HIGH BANDWIDTH CACHE-TO-PROCESSING UNIT COMMUNICATION IN A MULTIPLE PROCESSOR/CACHE SYSTEM  
A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact...
US20110002152 SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES  
Memories, systems, and methods for repairing are provided. A memory with extra digit lines in end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one...
US20080175032 SEMICONDUCTOR MEMORY AND METHOD FOR MANUFACTURING THE SAME  
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory including: a plurality of memory devices each having: a resistance change element, and a diode...