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US20060193187 Disk drive unit having reduced electrical power consumption  
A disk drive unit for a disk, e.g. for use in a mobile device, comprises a spindle (1) positioned within the disk drive unit and adapted to support the disk rotatably in an operating position. An...
US20110157962 BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE  
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices...
US20100182861 SENSE AMPLIFIER WITH A COMPENSATING CIRCUIT  
A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating...
US20140036579 SENSE AMPLIFIER  
Embodiments of the invention provide a sense amplifier, a SRAM chip comprising the sense amplifier and a method of performing read operation on the SRAM chip. The sense amplifier according to...
US20140241087 SENSE AMPLIFIER  
A sense amplifier comprises a cross coupled pair of inverters, a first transistor, a second transistor, and a capacitive device. The cross coupled pair of inverters includes a first end, a second...
US20070091701 Semiconductor device and a method of testing the same  
The present invention comprises first and second differential pairs (MN31, MN32), (MN33, MN34) to which first and second differential input signals (CIB0, CIT0), (CIB90, CIT90) are input, output...
US20080175084 SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER CIRCUIT  
A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits...
US20060181935 Semiconductor memory devices and methods of operating the same  
A semiconductor memory device may include a plurality of independently operated memory banks each including a plurality of wordlines. At least one of the plurality of wordlines may be activated in...
US20140003175 STORAGE CELL BRIDGE SCREEN TECHNIQUE  
A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when...
US20140241078 SEMICONDUCTOR MEMORY DEVICE  
A sense amplifier circuit is divided into a plurality of sense amplifier groups. The plurality of sense amplifier groups are each further divided into a plurality of sense units. A sense amplifier...
US20070217247 Shared sense amplifier for fuse cell  
An apparatus, a method, and a system for a fuse array are disclosed herein. In some embodiments, fuse array may comprise a plurality of fuse cells and a single sense amplifier coupled to plurality...
US20090268538 Current sensing circuit and semiconductor memory device including the same  
To provide a current sensing circuit that detects a difference between a cell current and a reference current. The current sensing circuit includes: current mirror circuits of which the input...
US20070121414 SHIELDED BITLINE ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARRAYS  
A shielded bitline architecture for DRAM memories and integrated circuit devices incorporating embedded DRAM is disclosed herein which comprises a shared sense amplifier, folded bitline array...
US20070223296 Bitline isolation control to reduce leakage current in memory device  
A semiconductor memory device and method are provided in which leakage current of the memory device is reduced. A sense amplifier is isolated from a memory array that has an anomalous bitline...
US20090180343 SEMICONDUCTOR MEMORY DEVICE  
A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further...
US20140198596 CIRCUIT FOR CONTROLLING SENSE AMPLIFIER SOURCE NODE IN SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD THEREOF  
Provided is a bit line sense amplifier source node control circuit of a semiconductor memory device. The sense amplifier source node control circuit may include a source driver connected between a...
US20070070748 Method for Discharging and Equalizing Sense Lines to Accelerate Correct MRAM Operation  
A method and apparatus for discharging and equalizing sense lines embedded in a magnetoresistive random access memory integrated circuit (MRAM IC) includes using a current source connected to a...
US20090238010 SYSTEMS AND DEVICES INCLUDING MULTI-TRANSISTOR CELLS AND METHODS OF USING, MAKING, AND OPERATING THE SAME  
Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data...
US20070247939 MRAM ARRAY WITH REFERENCE CELL ROW AND METHOF OF OPERATION  
A magnetoresistive random access memory (MRAM) avoids difficulties with write disturb by electrically isolating the portion of the array with data from the portion with reference signals while...
US20070070758 SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER AND SWITCH  
A method for operating a semiconductor memory and to a semiconductor memory with at least one sense amplifier and device for switching the sense amplifier to or off at least one line is disclosed....
US20070258304 Method and System for Preventing Noise Disturbance in High Speed, Low Power Memory  
A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the...
US20080031065 SEMICONDUCTOR MEMORY DEVICE WITH COLUMN TO BE SELECTED BY BIT LINE SELECTION SIGNAL  
A sense amplifier bank contains sense amplifier circuits, data line pairs and selection circuits. The selection circuits set one of a connection status and a disconnection status between a bit...
US20100054042 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF INSPECTING THE SAME  
A semiconductor memory device comprises a sense amplifier circuit having a first and a second input terminal, the sense amplifier configured to compare current flowing in the first input terminal...
US20080205180 Semiconductor memory device having bit-line sense amplifier  
A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes:...
US20130301364 SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE  
A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a...
US20070070756 Semiconductor memory device sharing sense amplifier  
A semiconductor memory device contains a reduced number of signal lines of a core area required for data access. The semiconductor memory device includes a sense amplifier for selectively sensing...
US20080043513 INTERGRATED CIRCUIT HAVING MEMORY WITH RESISTIVE MEMORY CELLS  
A memory device, and method of operating the same, wherein the device includes resistive memory cells being switched between a low-resistive state and a high-resistive state; an evaluation unit,...
US20080008019 High Speed Read-Only Memory  
A high speed read-only memory (ROM). Data stored in a memory cell in the ROM array is provided to a sense amplifier in a differential form. Two transistors storing complementary logic states form...
US20130135946 DUAL RAIL MEMORY ARCHITECTURE  
A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in...
US20110103136 SEMICONDUCTOR MEMORY DEVICE  
A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further...
US20120134227 SEMICONDUCTOR DEVICE HAVING SENSE AMPLIFIER  
For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the...
US20140269131 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS  
A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory...
US20090059686 Sensing scheme for the semiconductor memory  
The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and...
US20110128764 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor device includes a first amplifier circuit, a second amplifier circuit, first and second bit lines coupled to the first amplifier circuit, third and fourth bit lines coupled to the...
US20090279372 SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER  
In a sense amplifier circuit having a plurality of sense amplifier portions arranged in order, each of the sense amplifier portions includes a transistor that supplies a bit line potential to a...
US20080144367 Sensing device for floating body cell memory and method thereof  
A memory device includes a memory array and a sense amplifier. The memory array includes a floating body cell configured to store a bit value. The sense amplifier includes a bit output configured...
US20150171215 SEMICONDUCTOR DEVICE HAVING WAVE GATE  
A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed...
US20100067318 SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER  
A sense amplifier comprises: a differential amplifier circuit configured to generate an amplified signal depending on a difference in voltage between bit lines; an output circuit receiving the...
US20150085593 NON-VOLATILE MEMORY (NVM) WITH DYNAMICALLY ADJUSTED REFERENCE CURRENT  
A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored...
US20140146628 TECHNIQUE FOR IMPROVING STATIC RANDOM-ACCESS MEMORY SENSE AMPLIFIER VOLTAGE DIFFERENTIAL  
A static random-access memory (SRAM) module includes a column select (RSEL) driver coupled to an input/output (I/O) circuit by an RSEL line. The I/O circuit is configured to read bit line signals...
US20130163363 SYSTEMS AND METHODS OF NON-VOLATILE MEMORY SENSING INCLUDING SELECTIVE/DIFFERENTIAL THRESHOLD VOLTAGE FEATURES  
Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is...
US20100232244 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality...
US20100149850 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE  
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a memory cell array including: memory cell blocks each having...
US20100128513 SEMICONDUCTOR MEMORY DEVICE  
A memory cell array includes a memory cell comprising a ferroelectric capacitor and a transistor arranged therein. A plate line applies a drive voltage to one end of the ferroelectric capacitor. A...
US20100124134 Semiconductor device  
A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive...
US20090219749 METHOD AND APPARATUS FOR IMPLEMENTING CONCURRENT MULTIPLE LEVEL SENSING OPERATION FOR RESISTIVE MEMORY DEVICES  
An apparatus for sensing the data state of a multiple level, programmable resistive memory device includes an active clamping device connected to a data leg that is selectively coupled a...
US20080056041 MEMORY CIRCUIT  
A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each...
US20170178698 Memory Cell  
The present disclosure relates to a memory cell, a memory array, and methods for writing a memory cell. In an example embodiment, a memory cell comprises a first transistor, a second transistor,...
US20170133069 SEMICONDUCTOR MEMORY APPARATUS HAVING OPEN BIT LINE STRUCTURE  
A semiconductor memory apparatus may include a memory bank having a plurality of memory cell arrays. The memory bank may have an open bit line structure. A sense amplifier array may be coupled in...
US20170117032 SEMICONDUCTOR MEMORY DEVICE THAT VARIES VOLTAGE LEVELS DEPENDING ON WHICH OF DIFFERENT MEMORY REGIONS THEREOF IS ACCESSED  
A semiconductor memory device includes a semiconductor memory chip including a plurality of regions of memory cells, including a first memory region and a second memory region, and a memory...

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