Matches 1 - 50 out of 137 1 2 3 >


Match Document Document Title
US20090219743 Three dimensional structure memory  
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately...
US20090219742 Three dimensional structure memory  
A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately...
US20110310686 Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies  
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit...
US20070014168 Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies  
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit...
US20060227636 METHODS AND SYSTEMS FOR PROVIDING PAPER BASED OUTCOMES  
In various embodiments, gaming devices may generate outcomes to be sold in printed form. Representations of the outcomes, corresponding payouts, and other information are printed on sheets of...
US20050226067 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material  
A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very...
US20070165472 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM  
A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive...
US20140043924 CONFIGURABLE MEMORY ARRAY  
Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of...
US20140241076 SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME  
A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving...
US20050185485 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device  
By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the...
US20080205170 DDR-SDRAM INTERFACE CIRCUITRY, AND METHOD AND SYSTEM FOR TESTING THE INTERFACE CIRCUITRY  
According to one aspect of an embodiment of the present invention, there is provided a memory interface circuit including a first data output circuit which outputs a data signal based on a data...
US20050265083 Method and system for monitoring a supply-chain  
A method of monitoring supply chain activity throughout a plurality of supply chain sites includes extracting, at each supply chain site, supply-related data to be monitored. The data is...
US20060050580 Method for generating identification code of semiconductor device, method for identifying semiconductor device and semiconductor device  
A semiconductor device including memory cells such as flip-flops, RAMs or SRAMs is powered on, and first logic signals of Hi or Lo output from the respective memory cells are obtained. A...
US20090016130 MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE  
In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern,...
US20080266990 Flexible redundancy replacement scheme for semiconductor device  
A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme...
US20070047347 Semiconductor memory devices and a method thereof  
A semiconductor memory device and a method thereof are provided. The example method may include determining whether a currently tested cell is defective and repairing the currently tested cell, if...
US20050270869 Transistor  
A transistor has a cell array with two or more transistor cells, a temperature sensor, which is integrated in the cell array or is adjacent to the cell array, and an isolation structure. The...
US20140085995 METHOD, APPARATUS AND SYSTEM FOR DETERMINING A COUNT OF ACCESSES TO A ROW OF MEMORY  
Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the...
US20050135167 Memory access circuit for adjusting delay of internal clock signal used for memory control  
It is to form a memory access circuit comprising a memory, a clock generator for generating a reference clock signal, and a clock delay adjusting circuit for delaying the reference clock signal to...
US20120155192 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING THE SAME  
A semiconductor memory device and a method of testing the same are provided. The semiconductor memory device includes a memory cell array including a plurality of memory cells each of which stores...
US20110063909 NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF TESTING THE SAME  
A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory...
US20060265636 Optimized testing of on-chip error correction circuit  
The present invention includes a memory system with a data memory and a control circuit. The data memory has multiple memory segments, including a data memory array and a parity memory array. The...
US20070025167 Method for testing a memory device, test unit for testing a memory device and memory device  
A method, a memory device and a test unit to test such memory device is provided. The memory device comprises a memory cell array including a multitude of memory cells each having a variable...
US20100182857 TESTER FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
An apparatus testing a semiconductor device may include, but is not limited to, a first strobe signal generating circuit and a detecting circuit. The first strobe signal generating circuit...
US20100110786 Nonvolatile memory device, memory system including the same, and memory test system  
Provided are a nonvolatile memory device and a memory test system. The nonvolatile memory device includes a temperature compensator to calculate a trim value for regulating a characteristic of the...
US20160372161 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF  
A data storage device includes a nonvolatile memory apparatus including a target region; and a controller suitable for performing a read voltage adjustment operation including setting a plurality...
US20080106958 SEMICONDUCTOR CHIP PACKAGE AND METHOD AND SYSTEM FOR TESTING THE SAME  
A semiconductor chip package with a flash memory portion and a method and system for testing the same are provided. After an internal cycling test is automatically and independently initiated on...
US20110158017 METHOD FOR MEMORY CELL CHARACTERIZATION USING UNIVERSAL STRUCTURE  
A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage...
US20070030814 Memory module and method thereof  
A memory module and method thereof are provided. In the example method, a test signal may be applied to a plurality of memory chips included in the memory module. Output data from the plurality of...
US20130215696 ANTI-FUSE CIRCUIT OF SEMICONDUCTOR DEVICE AND METHODS OF TESTING INTERNAL CIRCUIT BLOCK THEREOF  
A method of testing an internal circuit block of anti-fuse circuit and a circuit for detecting a defect in the operation of the internal circuit block such as a defect in a sensing part or in a...
US20080159031 PARALLEL READ FOR FRONT END COMPRESSION MODE  
Methods and apparatus for increasing front-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the reduced number...
US20060253723 Semiconductor memory and method of correcting errors for the same  
A semiconductor memory employs the redundancy memory technique and the error correction code technique and method of correcting errors. The method of correcting errors reads data bits and a...
US20060203581 Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions  
An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the...
US20150019767 SEMICONDUCTOR MEMORY DEVICE HAVING DATA COMPRESSION TEST CIRCUIT  
A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global...
US20080285358 Method and circuit for stressing upper level interconnects in semiconductor devices  
A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the...
US20080198674 Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit  
A method for testing an integrated circuit having an array of resistivity changing cells, wherein the method includes selecting a plurality of cells, setting the state of each selected cell to a...
US20090103350 Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit  
According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a...
US20080259695 Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices  
A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input...
US20130163356 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT  
A semiconductor integrated circuit includes a plurality of memory cells, a plurality of receivers, each of the plurality of receivers being provided for a corresponding one of a plurality of units...
US20100008170 Semiconductor tester and testing method of semiconductor memory  
The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a...
US20080013389 Random access memory including test circuit  
A random access memory including input pads and a test circuit. The input pads are configured to receive a row address and a column address. The test circuit is configured to receive the row...
US20140226423 DEVICE  
Provided is a device, including: a first terminal which receives an external clock signal; a clock generation circuit connected to the first terminal to generate an internal clock signal based on...
US20090287362 MONITORED BURN-IN TEST APPARATUS AND MONITORED BURN-IN TEST METHOD  
A monitored burn-in test method includes: subjecting an element set, including elements, to a writing process for writing data into each of the elements, the elements requiring a refresh process;...
US20080298148 Semiconductor memory device and test method therefor  
There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test...
US20100195396 SEMICONDUCTOR MEMORY DEVICE AND SELF-TEST METHOD OF THE SAME  
A semiconductor memory device includes a main memory includes a nonvolatile memory, and a buffer which stores input/output data of the nonvolatile memory, a buffer unit of the main memory, the...
US20080165599 DESIGN STRUCTURE USED FOR REPAIRING EMBEDDED MEMORY IN AN INTEGRATED CIRCUIT  
A design structure for correcting embedded memory that has been identified as being defective by a memory controller. The address of the defective memory is provided by the memory controller to...
US20070076495 Wafer-level burn-in test method, wafer-level burn-in test apparatus and semiconductor memory device  
A wafer-level burn-in test for a write operation to memory cells is disclosed. The memory cells are associated with a column switch transistor having a gate. In accordance with the method, a...
US20090021996 Memory Circuit, Memory Component, Data Processing System and Method of Testing a Memory Circuit  
A memory circuit includes a plurality of bit lines and a plurality of memory cells which may be written to via a respective bit line. The memory circuit further includes a bit line control...
US20080080284 METHOD AND APPARATUS FOR REFRESHING MEMORY CELLS OF A MEMORY  
Method and apparatus for refreshing selective memory cells. A refresh circuit is connected with the memory cells and operates to refresh data stored in the memory cells on the basis of the values...
US20060044899 Method and apparatus for destroying flash memory  
On command and subject to a fail-safe interlock, a signal is generated to essentially instantaneously destroy the data and/or access to data stored in a flash memory device. Subsequently, the...

Matches 1 - 50 out of 137 1 2 3 >