Matches 1 - 49 out of 49


Match Document Document Title
US20080219068 ZQ CALIBRATION CONTROLLER AND METHOD FOR ZQ CALIBRATION  
A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a...
US20090190421 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM FOR COMPENSATING CROSSTALK  
A semiconductor memory device and a semiconductor memory system. The semiconductor memory device includes channels configured to transmit signals from a transmitter to a receiver, and a crosstalk...
US20060274598 METHOD FOR CONTROLLING THE ACCESS TIMES TO A SYSTEM BUS AND COMMUNICATION MODULE  
A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module,...
US20100054055 DATA INPUT/OUTPUT CIRCUIT  
A data input/output circuit includes an output unit for outputting a first data strobe signal and first data in response to an internal clock generated in a delay locked loop, a first transmission...
US20100054047 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus includes a clock generator configured to generate an internal clock signal, an asynchronous data input buffer configured to buffer a data input signal through a...
US20090116316 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE  
Semiconductor device and semiconductor memory device include a plurality of internal circuits configured to perform test operations in response to their respective test mode signals and a...
US20100039871 SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY  
A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the...
US20090273995 APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE  
An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the...
US20140185384 NONVOLATILE MEMORY DEVICES INCLUDING SIMULTANEOUS IMPEDANCE CALIBRATION  
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration...
US20100027356 Dynamic On-Die Termination of Address and Command Signals  
A system includes a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry for connection to an address and control (RQ)...
US20060018185 Memory control apparatus and electronic apparatus  
In order to control a synchronous memory, a synchronous signal is required. In most cases, a clock signal is used for this purpose. This approach has room for improvement in power consumption etc....
US20100220537 ACTIVE TERMINATION CIRCUIT AND METHOD FOR CONTROLLING THE IMPEDANCE OF EXTERNAL INTEGRATED CIRCUIT TERMINALS  
An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor...
US20070091696 Memory controller  
The present invention relates to a memory controller for an IC with an external DRAM, where the external DRAM has at least one memory bank and communicates with the IC via at least one channel. In...
US20140301134 GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT  
A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced...
US20100142242 READ AND MATCH CIRCUIT FOR LOW-VOLTAGE CONTENT ADDRESSABLE MEMORY  
The present invention discloses a read and match circuit for a low-voltage content addressable memory, wherein the write circuit inputs the signals needing storing into the memory cells, and the...
US20110128797 SENSE AMPLIFYING CIRCUIT, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME  
A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first...
US20100202227 REFERENCE VOLTAGE AND IMPEDANCE CALIBRATION IN A MULTI-MODE INTERFACE  
A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the...
US20120250436 IMPEDANCE MATCHING BETWEEN FPGA AND MEMORY MODULES  
Embodiments of the present invention provide impedance matching between a Field Programmable Gate Array (FPGA) and memory modules in a semiconductor storage device (SSD) system architecture....
US20100277994 Semiconductor Memory Device and Operating Method Thereof  
A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The...
US20100246296 Write Driver and Semiconductor Memory Device Using the Same  
A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank...
US20100246292 Cell Inferiority test circuit  
A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information...
US20100246287 STORAGE DEVICES WITH SOFT PROCESSING  
A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage...
US20100142297 DATA DRIVER  
A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation...
US20100124129 DATA WRITING APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT  
A data writing apparatus includes a distributed transmission unit configured to transmit first data and second data, having been aligned to have the same timing, to data lines at mutually...
US20160315614 MEMORY MODULES  
A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or...
US20150206825 SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA  
A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block...
US20150124541 MEMORY CARD AND SD CARD  
According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which...
US20150103609 SEMICONDUCTOR DEVICES  
A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of...
US20150098285 ON-DIE TERMINATION APPARATUSES AND METHODS  
Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory die is addressed to another memory...
US20140204692 SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY  
A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the...
US20140169112 SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF  
A semiconductor memory system configured to exchange signals through channels may include a memory control device configured to have a plurality of channels, a plurality of memory devices...
US20140140152 SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF  
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a...
US20130242680 MEMORY MODULES  
A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or...
US20120281486 SEMICONDUCTOR MEMORY DEVICE AND METHOD WITH AUXILIARY I/O LINE ASSIST CIRCUIT AND FUNCTIONALITY  
A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the...
US20120218832 DATA TRANSMISSION CIRCUIT  
A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to...
US20120081982 VERIFYING A DATA PATH IN A SEMICONDUCTOR APPARATUS  
A semiconductor apparatus includes a memory array configured to store write data transmitted through data transmission lines and transmit stored data to the data transmission line as read data; a...
US20120026807 SEMICONDUCTOR MEMORY CHIP AND INTEGRATED CIRCUIT  
A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with...
US20110305097 Semiconductor device and data processing system  
A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the...
US20110249483 STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE  
A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a...
US20110242916 ON-DIE TERMINATION CIRCUIT, DATA OUTPUT BUFFER AND SEMICONDUCTOR MEMORY DEVICE  
An on-die termination circuit includes a termination resistor unit connected to an external pin, and a termination control unit connected to the termination resistor unit. The termination resistor...
US20110216613 LOW POWER TERMINATION FOR MEMORY MODULES  
An apparatus is provided that includes a memory controller to provide a first on-die termination (ODT) signal and a second ODT signal, a memory channel, a first memory module to couple to the...
US20110158011 SEMICONDUCTOR MEMORY INTERFACE DEVICE AND METHOD  
A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output...
US20110116331 METHOD FOR INITIALIZING MEMORY DEVICE  
A method for initializing a memory device is provided. The method includes a step for transmitting at least N+1 clock cycles to the memory device, wherein the N is an amount of bits of output...
US20110110168 SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device, a semiconductor memory module, and a semiconductor memory system including the same, the semiconductor memory device including a command/address input buffer that...
US20110103171 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column...
US20110103162 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a...
US20110103160 SEMICONDUCTOR MEMORY APPARATUS  
A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a...
US20110044120 SEMICONDUCTOR DEVICE  
A semiconductor device includes a data transmission line and a data transmission line precharge circuit. The data transmission line precharge circuit sets a precharge potential of the data...
US20100302886 MAT COMPRESS CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME  
A mat compress circuit includes a pre-control signal generator that generates a first pre-control signal and a second pre-control signal alternatively activated in response to an up/down bank...

Matches 1 - 49 out of 49