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US20140293717 |
MEMORY DEVICES AND METHODS FOR HIGH RANDOM TRANSACTION RATE
A memory device can include a random access memory array configured to store data values; a plurality of bi-directional ports, configured to transfer data values into and out of the memory device... |
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US20140043924 |
CONFIGURABLE MEMORY ARRAY
Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of... |
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US20140226421 |
CLOCK SIGNAL GENERATION APPARATUS FOR USE IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD
A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a... |
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US20130215659 |
LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME
A device includes a printed circuit board, a clock connector provided on the printed circuit board and configured to be supplied with a first clock signal, a first register buffer provided on the... |
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US20150262643 |
VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are... |
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US20090213659 |
FLASH MEMORY DEVICE AND FLASH MEMORY SYSTEM INCLUDING THE SAME
A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to... |
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US20100157644 |
Configurable memory interface to provide serial and parallel access to memories
The invention relates to an interface for providing multiple modes of accessing data, including serial and parallel modes. Controllable non-volatile memory interfaces are described, including a... |
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US20100214831 |
Memory device, memory system having the same, and programming method of a memory cell
A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second... |
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US20130194881 |
AREA-EFFICIENT MULTI-MODAL SIGNALING INTERFACE
One or more pins may be modally assigned to either the command/address (C/A) or data (DQ) blocks of a uniform-package, multi-modal PHY (physical signaling interface) of a memory controller, thus... |
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US20150103608 |
SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME
A device including input and output nodes, first and second input circuits coupled in parallel to each other between the input and output nodes. The first input circuit includes a first circuit... |
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US20140233334 |
SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME
A device includes a command decoder that is configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active... |
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US20100110753 |
Ferroelectric Memory Cell Arrays and Method of Operating the Same
An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated... |
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US20080084769 |
Memory system and method for operating a memory system
A memory system, in particular a buffered memory system, e.g. a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. In one... |
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US20090196107 |
SEMICONDUCTOR DEVICE AND ITS MEMORY SYSTEM
A semiconductor device selects one mask pattern among from a plurality of the mask patterns, which are stored in a mask resister circuit for mask controlling of a bit width (vertical axis), by a... |
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US20140169110 |
Clock Synchronization In A Memory System
Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is... |
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US20080080267 |
DATA OUTPUT CONTROL CIRCUIT AND DATA OUTPUT CONTROL METHOD
A data output control circuit controls a data output in a read operation. A data output control method includes a count shifting mode and a delay mode and can be used in low and high frequency... |
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US20100118582 |
MEMORY MODULE AND MEMORY SYSTEM HAVING THE SAME
A memory module comprises of a plurality of memory chips arranged in a rank and configured to input and output data in response to at least one of a command signal and an address signal. The... |
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US20120250434 |
METHOD OF ACCELERATING WRITE TIMING CALIBRATION AND WRITE TIMING CALIBRATION ACCELERATION CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE
A method of accelerating write timing calibration and a write timing calibration acceleration circuit in a semiconductor memory device are disclosed. The write timing calibration acceleration... |
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US20100074035 |
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for... |
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US20050213399 |
Method and apparatus to write data
Briefly, in accordance with an embodiment of the invention, a method and apparatus to write data is provided. The apparatus may include a circuit to deassert a chip select signal to latch data in... |
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US20080259695 |
Semiconductor Memory Devices Having a Demultiplexer and Related Methods of Testing Such Semiconductor Memory Devices
A semiconductor memory device includes a memory cell array and a demultiplexer that has a first input port that is configured to receive both an address signal and a data signal and a second input... |
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US20100220514 |
STORAGE DEVICES WITH SOFT PROCESSING
A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage... |
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US20140328130 |
INTEGRATED CIRCUIT WITH BUMP CONNECTION SCHEME
An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant... |
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US20080181030 |
MEMORY SYSTEM, MEMORY DEVICE AND COMMAND PROTOCOL
A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set... |
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US20110242869 |
THREE-DIMENSIONAL STACKED SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD THEREOF
A three-dimensional stacked semiconductor integrated circuit including a plurality of stacked chips. The semiconductor integrated circuit is configured to simultaneously select the plurality of... |
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US20140233332 |
SEMICONDUCTOR MEMORY SYSTEM
A semiconductor memory system includes a semiconductor memory configured to provide an external circuit with a plurality of refresh characteristic information and perform an auto-refresh operation... |
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US20110103156 |
DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME
A data input/output circuit includes a rank selecting section and a data input/output section. The rank selecting section is selectively connected to one of the first and second ranks in response... |
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US20090303809 |
CIRCUIT AND METHOD FOR TERMINATING DATA LINE OF SEMICONDUCTOR INTEGRATED CIRCUIT
A data line termination circuit in a semiconductor integrated circuit includes a data line, a control unit for generating a termination control signal activated during a time section that includes... |
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US20130135948 |
SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device according to an embodiment includes: a memory cell in which data is stored; a word line through which the memory cell is selected in each row; a bit line through... |
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US20120224441 |
SEMICONDUCTOR MEMORY APPARATUS
Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a semiconductor memory apparatus may include a page size control unit configured to generate... |
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US20060120181 |
Fault detection and isolation with analysis of built-in-test results
A method for detecting and isolating faults in a complex system using a meta-analysis of subsystem built-in-test (BIT) results is disclosed. Subsystem BIT results may be combined with each other... |
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US20090059691 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND MULTI TEST METHOD THEREOF
A semiconductor integrated circuit includes a multi-mode control signal generating section that enables one of up and down mat input/output switch control signals for controlling input/output... |
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US20160042772 |
SEMICONDUCTOR DEVICES
A semiconductor device may include a first input/output unit and a second input/output unit. The first input/output unit may operate in synchronization with an internal clock signal to output a... |
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US20120213018 |
DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to... |
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US20100195420 |
SEMICONDUCTOR MEMORY DEVICE AND SYSTEM
A semiconductor memory system includes a memory controller and a memory. The memory controller includes a control signal converting unit converting a control signal into a converted control signal... |
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US20130128678 |
POWER SAVING METHODS FOR USE IN A SYSTEM OF SERIALLY CONNECTED SEMICONDUCTOR DEVICES
A semiconductor device comprising (i) internal circuitry for outputting at least one internal clock signal and at least one internal data/control signal for transmission to a next device in a... |
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US20090230992 |
DATA TRANSMISSION CIRCUIT CAPABLE OF REDUCING CURRENT CONSUMPTION
A data transmission circuit includes a first signal transmission unit and a second signal transmission unit. The first signal transmission unit includes a driving unit having a plurality of... |
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US20140355365 |
PULSE GENERATOR
Various circuits and methods of operating circuits are disclosed. A circuit may include a pulse generator and a latch having an output configured to trigger the pulse generator, wherein the latch... |
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US20100202221 |
METHOD OF READING MEMORY CELL
A method for reading a memory cell (20) of a semiconductor memory (10) includes initiating a precharge or predischarge operation on a bit line (24) prior to arrival of a triggering edge of a clock... |
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US20080043544 |
Memory device and method of improving the reliability of a memory device
A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being... |
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US20150235678 |
ADAPTIVE CONTROL METHOD BASED ON INPUT CLOCK AND RELATED ADAPTIVE CONTROLLED APPARATUS
An adaptive control method based on an input clock includes: performing a read process according to the input clock; receiving a read command; receiving a data signal via a data line according to... |
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US20110022808 |
OUTPUT DRIVER, MEMORY HAVING OUTPUT DRIVER, MEMORY CONTROLLER, AND MEMORY SYSTEM
An output driver has a first driver connected between a first power source and an output terminal and a second driver connected between a second power source and the output terminal. One of the... |
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US20110249510 |
EMBEDDED STORAGE APPARATUS AND TEST METHOD THEREOF
An embedded storage apparatus including a control unit, a storage unit, and a signal processing and measurement unit is provided. The control unit outputs a plurality of signals, wherein the... |
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US20100142293 |
Boosting voltage generating circuit, negative voltage generating circuit, step-down voltage generating circuit, and semiconductor device
In a boosting voltage generating circuit, a boosting circuit unit generates boosting voltage according to a value of boosting voltage output by the boosting voltage generating circuit and an... |
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US20070121392 |
Nonvolatile semiconductor memory device and its writing method
There is provided a nonvolatile semiconductor memory device and its writing method capable of controlling an increase in threshold voltage due to effects of adjacent memory cells and performing... |
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US20160260470 |
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM
A semiconductor system may include a first semiconductor configured to output a command signal and an address signal. The semiconductor system may include a second semiconductor device configured... |
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US20160012871 |
INTEGRATED CIRCUIT FOR STORING INFORMATION
An integrated circuit includes a variable resistance unit including at least one transistor that receives a control signal and changes a resistance through the transistor in response to the... |
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US20120275243 |
SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes: a first switch configured to couple a bit line to a first input/output line in response to an output selection signal including a pulse which is generated... |
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US20100054054 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
A semiconductor memory device includes a plurality of word lines and a plurality of pairs of bit lines and complementary bit lines that cross the plurality of word lines. A plurality of memory... |
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US20110261614 |
Semiconductor device
A semiconductor device that needs a relatively long time to control a write operation and the like is reduced in size. The semiconductor device includes: first and second bit line control circuits... |