Matches 1 - 21 out of 21


Match Document Document Title
US20080205169 DEVICE FOR STORING A BINARY STATE  
Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in...
US20090073786 EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICES AND THOSE INCORPORATING EMBEDDED DRAM  
An early write with data masking technique for dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM. The technique of the present invention allows for early...
US20130229883 SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES  
A memory with extra digit lines in full size end arrays with an open digit architecture, which can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are...
US20130010551 SYSTEMS, MEMORIES, AND METHODS FOR REPAIR IN OPEN DIGIT MEMORY ARCHITECTURES  
A memory with extra digit lines in full size end arrays with an open digit architecture can use the extra digit lines to form repair cells. In one example, folded digit sense amplifiers are...
US20080316842 SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR BROADCASTING WRITE OPERATIONS  
A system, method, and computer program product are provided for broadcasting write operations in a multiple-target system. In use, a write operation is received at one of a plurality of apertures...
US20070177439 Displaying supply information of an image forming apparatus  
An apparatus, method, system, computer program and product, each capable of managing supply information of an image forming device provided in an image forming apparatus, and displaying the supply...
US20140153347 INPUT-OUTPUT LINE SENSE AMPLIFIER HAVING ADJUSTABLE OUTPUT DRIVE CAPABILITY  
An input-output line sense amplifier configured to drive input data signals over an input-output signal line to an output driver circuit, the input-output line sense amplifier having an output...
US20080273402 APPARATUS FOR IMPLEMENTING DOMINO SRAM LEAKAGE CURRENT REDUCTION  
A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of...
US20120230134 DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE  
The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a...
US20080285370 Semiconductor memory and system  
An access control unit performs an access operation and a refresh operation of a memory block in response to an access request and a refresh request. The access control unit operates respective...
US20130235678 NON-VOLATILE MEMORY ARRAY ARCHITECTURE OPTIMIZED FOR HI-RELIABILITY AND COMMERCIAL MARKETS  
A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is...
US20100177576 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line...
US20100128546 Embedded Memory Databus Architecture  
A dynamic random access memory (DRAM) having pairs of bitlines, each pair being connected to a first bit line sense amplifier, wordlines crossing the bitlines pairs forming an array, charge...
US20090231939 Circuit and Method for a Vdd Level Memory Sense Amplifier  
A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense...
US20150170717 Method, Apparatus and Device for Data Processing  
An embodiment relates to a method for data processing and comprises determining an electrical variable for each cell of a data bit, transforming each electrical variable into the time domain, and...
US20130272078 STORAGE CONTROLLING APPARATUS, MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROLLING METHOD  
Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a...
US20130265834 APPARATUSES AND METHODS FOR IMPROVED MEMORY OPERATION TIMES  
Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense amplifier is directly coupled to the...
US20130088912 SEMICONDUCTOR MEMORY DEVICE  
A semiconductor memory device includes a first bit line to which a first memory cell is connected, and a second bit line to which a second memory cell is connected, the second bit line being...
US20120300560 SEMICONDUCTOR MEMORY DEVICES INCLUDING PRECHARGE USING ISOLATED VOLTAGES  
A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells...
US20110069566 MEMORY CELL WRITE  
Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first...
US20110013467 System and Method for Reading Memory  
A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the...

Matches 1 - 21 out of 21