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US20090080245 |
OFFSET NON-VOLATILE STORAGE
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce... |
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US20110286265 |
PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING
A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process... |
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US20120307558 |
APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as... |
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US20130258771 |
METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE
In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the... |
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US20150213904 |
Reduction of Read Disturb Errors
Methods and apparatuses for reduction of read disturb errors in a memory system utilizing modified or extra memory cells. |
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US20140301140 |
Reduction of Read Disturb Errors
Methods and apparatuses for reduction of Read Disturb errors in a memory system utilizing modified or extra memory cells. |
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US20140313822 |
GROUP CLASSIFICATION METHOD FOR SOLID STATE STORAGE DEVICE
A group classification method includes the following steps. Firstly, a voltage shift parameter table is established. The voltage shift parameter table includes a first positional parameter table... |
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US20120262986 |
SOURCE SIDE ASYMMETRICAL PRECHARGE PROGRAMMING SCHEME
A method for programming NAND flash cells to minimize program stress while allowing for random page programming operations. The method includes asymmetrically precharging a NAND string from a... |
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US20090323412 |
READ DISTURB MITIGATION IN NON-VOLATILE MEMORY
Read disturb is reduced in non-volatile storage. In one aspect, when a read command is received from a host for reading a selected word line, a word line which is not selected for reading is... |
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US20110249494 |
MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for... |
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US20100329002 |
FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION
Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a... |
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US20090034328 |
MEMORY SYSTEM PROTECTED FROM ERRORS DUE TO READ DISTURBANCE AND READING METHOD THEREOF
A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to... |
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US20080151618 |
Flash memory device and system with randomizing for suppressing errors
A device for storing data includes a nonvolatile memory and a controller and/or circuitry that randomize original data to be stored in the memory while preserving the size of the original data,... |
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US20100302844 |
METHOD AND APPARATUS FOR PROVIDING A NON-VOLATILE MEMORY WITH REDUCED CELL CAPACITIVE COUPLING
A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally... |
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US20110122689 |
REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE
A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word... |
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US20150262657 |
TWO-PART PROGRAMMING METHODS
Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher... |
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US20080158948 |
AVOIDING ERRORS IN A FLASH MEMORY BY USING SUBSTITUTION TRANSFORMATIONS
To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of... |
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US20120140557 |
PROGRAMMING METHOD FOR NON-VOLATILE MEMORY DEVICE
Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a... |
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US20100128521 |
APPLYING NEGATIVE GATE VOLTAGE TO WORDLINES ADJACENT TO WORDLINE ASSOCIATED WITH READ OR VERIFY TO REDUCE ADJACENT WORDLINE DISTURB
Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or... |
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US20100188897 |
APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB
The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as... |
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US20110032757 |
Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage
Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage... |
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US20090172254 |
METHOD FOR PREVENTING READ-DISTURB HAPPENED IN NON-VOLATILE MEMORY AND CONTROLLER THEREOF
A method for preventing read-disturb happened in non-volatile memory and a controller thereof are disclosed. The non-volatile memory includes a plurality of blocks, and the blocks are grouped into... |
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US20150070985 |
Linear Programming Based Decoding For Memory Devices
Technologies are generally described herein for linear programming based decoding for memory devices. In some examples, a cell threshold voltage level of a memory cell is detected. An interference... |
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US20140244905 |
Linear Programming Based Decoding for Memory Devices
Technologies are generally described herein for linear programming based decoding for memory devices. In some examples, a cell threshold voltage level of a memory cell is detected. An interference... |
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US20090067234 |
Flash Memory Device and Fabrication Method Thereof
The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate... |
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US20130088916 |
DISTURB VERIFY FOR PROGRAMMING MEMORY CELLS
Apparatuses and methods for disturb verify for programming operations are described. Programming memory cells can include applying a number of programming pulses to a first memory cell, performing... |
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US20140369117 |
MULTIPLE STEP PROGRAMMING IN A MEMORY DEVICE
Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If the programmed threshold voltage is... |
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US20130343123 |
FLASHMEMORY PROGRAM INHIBIT SCHEME
A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted... |
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US20090180316 |
System and Devices Including Memory Resistant to Program Disturb and Methods of Using, Making, and Operating the Same
Disclosed are methods, systems and devices, one such device being a memory device configured to concurrently assert a first pulse pattern through a plurality of conductors disposed on both a... |
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US20080106935 |
Non-volatile semiconductor memory device using weak cells as reading identifier
A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile... |
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US20090129146 |
MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to... |
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US20150055411 |
METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE HAVING READ DISTURBED PAGE
A method of operating a nonvolatile memory device by programming pages using a N-bit programming mode until a threshold voltage distribution shift for an un-programmed page in the same memory... |
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US20130301351 |
Channel Boosting Using Secondary Neighbor Channel Coupling In Non-Volatile Memory
In a non-volatile storage system, a programming portion of a program-verify iteration has multiple programming pulses, and storage elements along a word line are selected for programming according... |
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US20110075477 |
REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING
A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example,... |
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US20140307505 |
MEMORY DISTURB REDUCTION FOR NONVOLATILE MEMORY
Technology is described that supports reduced program disturb of nonvolatile memory. A three/two dimensional NAND array includes a plurality of pages, which are divided into a plurality of page... |
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US20110216586 |
Methods And Apparatus For Intercell Interference Mitigation Using Modulation Coding
Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more... |
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US20130163325 |
NON-VOLATILE MEMORY DEVICE, METHOD FOR FABRICATING THE SAME, AND METHOD FOR OPERATING THE SAME
A non-volatile memory device includes a first string and a second string that each include a first drain selection transistor, a second drain selection transistor, a plurality of memory cells, and... |
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US20120236640 |
REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the... |
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US20150103594 |
INTER-CELL INTERFERENCE CANCELLATION
A read module reads memory cells along a first word line by applying a plurality of threshold voltages to the first word line; generates first information about a first memory cell located along... |
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US20090251962 |
Three-Dimensional Memory Device and Driving Method Thereof
A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A... |
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US20140063938 |
NONVOLATILE MEMORY DEVICE AND SUB-BLOCK MANAGING METHOD THEREOF
A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate,... |
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US20140098606 |
REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge... |
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US20150003151 |
NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ
This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block... |
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US20100135075 |
READING NON-VOLATILE MULTILEVEL MEMORY CELLS
Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile multilevel memory cells. One method includes receiving a request to read data stored... |
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US20080198650 |
Distortion Estimation And Cancellation In Memory Devices
A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels... |
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US20150131373 |
Incremental Programming Pulse Optimization to Reduce Write Errors
In a data storage system having multi-level memory cells, a counter tracks the number of program/erase cycles, anticipated read cycles, or anticipated length of data retention of a cell. When a... |
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US20110128782 |
REDUCING EFFECTS OF ERASE DISTURB IN A MEMORY DEVICE
Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a... |
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US20090154232 |
Disturb control circuits and methods to control memory disturbs among multiple layers of memory
Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for controlling memory disturbs to and among... |
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US20090059660 |
REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING
A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example,... |
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US20100142268 |
PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY
A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory... |