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US20120218811 Circuit  
An object of the current invention is to provide DRAM that is not limited by capacitors.
US20090268508 Reverse leakage reduction and vertical height shrinking of diode with halo doping  
One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different...
US20080230763 Metallic Nanospheres Embedded in Nanowires Initiated on Nanostructures and Methods for Synthesis Thereof  
A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there...
US20090034327 THERMAL-EMITTING MEMORY MODULE, THERMAL-EMITTING MODULE SOCKET, AND COMPUTER SYSTEM  
The invention provides a thermal-emitting memory module, a thermal-emitting module socket, and a computer system comprising the thermal-emitting memory module and the thermal-emitting module...
US20090185413 SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH OUTPUT PATH CONTROL UNIT  
A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes...
US20090207654 Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same  
Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality...
US20100052729 DIGITAL DATA INVERSION FLAG GENERATOR CIRCUIT  
An integrated circuit includes an array of memory cells and a digital flag generator circuit configured to generate a data inversion flag based on whether a number of logical zero bits contained...
US20070247495 Continuous injet printers  
The invention provides a method of forming a charge electrode array for a binary continuous inkjet printer, the method including forming the charge electrodes and the driver circuitry for the...
US20070291534 An Electronic Communication Device with a Dynamic Multifunctional Module  
The invention relates to a dynamic multifunctional module and to an electronic communication device comprising a main body part, a sliding body part, said parts being connected together with...
US20080165568 Probes and Media for High Density Data Storage  
A device in accordance with embodiments of the present invention comprises a contact probe for high density data storage reading, writing, erasing, or rewriting. In one embodiment, the contact...
US20090003030 METHODS FOR FERROELECTRIC DOMAIN READING  
Methods and arrangements for data storage are discussed. Embodiments include applying a first voltage between a tip and an electrode, thereby forming a polarized domain in a ferroelectric material...
US20080266935 DRAM STORAGE CAPACITOR WITHOUT A FIXED VOLTAGE REFERENCE  
In one embodiment, a DRAM is provided that includes a plurality of memory cells, each memory cell including an access transistor and a storage capacitor, wherein the storage capacitor includes a...
US20080219044 Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory  
Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read...
US20080002452 Method for setting a read voltage, and semiconductor circuit arrangement  
A method for setting a read voltage that is used to read data from a nonvolatile memory is disclosed. Logic states from the first state set are stored in a particular number of digits in the...
US20090086535 SEMICONDUCTOR ARRAY  
A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines...
US20110032743 Colloidal-Processed Silicon Particle Device  
Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second...
US20090175073 Nanostructure-Based Memory  
Improved memory devices that include one or more nanostructures such as carbon nanotubes or other nanostructures, as well as systems and devices incorporating such improved memory devices, are...
US20120009976 RECESS GATE TRANSISTOR  
A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the...
US20090073758 SRAM CELLS WITH ASYMMETRIC FLOATING-BODY PASS-GATE TRANSISTORS  
The embodiments of the invention provide SRAM cells with asymmetric floating-body pass-gate transistors. More specifically, a semiconductor device includes an SRAM cell, a first pass-gate...
US20090067220 Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor  
A semiconductor device has a first inverter including a drive transistor and a load transistor; a second inverter including a drive transistor and a load transistor, a transmission transistor...
US20090103367 ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY  
Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be...
US20110170343 DRAM MEMORY CELL HAVING A VERTICAL BIPOLAR INJECTOR  
The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a...
US20100135071 MICROELECTRONIC PROGRAMMABLE DEVICE AND METHODS OF FORMING AND PROGRAMMING THE SAME  
A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of...
US20100054018 SEMICONDUCTOR MEMORY DEVICE AND INFORMATION PROCESSING SYSTEM  
A semiconductor memory device comprises a memory cell array and a forming controller. The memory cell array includes a plurality of first memory cells each having a structure in which dielectric...
US20090249167 Semiconductor memory device  
A semiconductor memory device includes a data storage area wherein a plurality of data cells, respectively storing one bit of data, is arranged in a lattice form, a redundant data storage area...
US20080192535 Sense amplifiers and semiconductor devices including the same  
A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second...
US20080316831 Nonvolatile semiconductor device, system including the same, and associated methods  
A nonvolatile memory device is provided. The nonvolatile memory device includes a semiconductor substrate and memory cell units arranged in a matrix on the semiconductor substrate. Each of the...
US20070159879 Method and system for probing FCode in problem state memory  
A method and system for probing FCode in problem state memory. A PCI device is detected from a PCI-PCI bridge node included in a device tree. A child node for the detected PCI device is created in...
US20080285337 RECORDABLE ELECTRICAL MEMORY  
A memory device includes memory cells each having a recordable layer between two metal layers, each memory cell being constructed and designed to change from a first state to a second state upon...
US20090048819 Multiple-type memory  
A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to...
US20100302854 Area-Efficient Electrically Erasable Programmable Memory Cell  
Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a...
US20100046304 NON-VOLATILE MEMORY DEVICE AND ERASE METHOD  
Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first...
US20070086237 Shape memory device  
Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in...
US20090102751 MEMORY ELEMENT AND DISPLAY DEVICE  
The present invention provides a memory element includes a thin film transistor configured to have a semiconductor thin film and a pair of gate electrodes that vertically sandwich the...
US20100034041 METHOD OF OPERATING SEMICONDUCTOR MEMORY DEVICE WITH FLOATING BODY TRANSISTOR USING SILICON CONTROLLED RECTIFIER PRINCIPLE  
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing...
US20080007997 Pmc Memory With Improved Retention Time And Writing Speed  
The invention concerns a PMC memory comprising a memory cell (4, 6, 8, 10) and means (16, 18, 20) for heating the cell when being written into the memory.
US20100302848 TRANSISTOR HAVING PERIPHERAL CHANNEL  
Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a channel region, and a second source/drain...
US20100091543 SEMICONDUCTOR MEMORY APPARATUS INCLUDING A COUPLING CONTROL SECTION  
A semiconductor memory apparatus is disclosed having a dual open bit line structure In the dual open bit line structure, bit lines or bit line bars are each arranged side by side in adjoining cell...
US20130235654 METHOD, SYSTEM, AND DEVICE FOR BASE CONTACT LAYOUT, SUCH AS FOR MEMORY  
Embodiments disclosed herein may relate to forming a base contact layout in a memory device.
US20080080251 Method of reading dual-bit memory cell  
A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage...
US20100046269 Programmable read only memory  
An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is...
US20090059678 Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device  
In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory...
US20090310424 METHOD OF ERASING A FLASH EEPROM MEMORY  
The invention is a new method for erasing a flash EEPROM memory device. The memory device has a first semiconductor region within a second semiconductor region, source and drain regions in the...
US20070189067 Dynamic memory  
Device for information storage. A preferred embodiment comprises a memory with a plurality of memory cells, with each memory cell comprising a thyristor. The thyristor has three terminals: an...
US20090003051 Semiconductor Memory Device and Semiconductor Device  
The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose...
US20090251959 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF  
A memory includes: memory cells including floating bodies, wherein in a data holding state, a potential of the first gate electrode is set to be higher than one of potentials of the source and...
US20090122613 Non-volatile memory device and method of operating the same  
A non-volatile memory device may include a plurality of stacked semiconductor layers, a plurality of NAND strings, a common bit line, a common source line, and/or a plurality of string selection...
US20090273962 FOUR-TERMINAL MULTIPLE-TIME PROGRAMMABLE MEMORY BITCELL AND ARRAY ARCHITECTURE  
Embodiments disclosed herein relate to a non-volatile memory bitcell and arrays thereof, methods of detecting whether the bitcell is in a programmed state, methods of detecting whether the bitcell...
US20100097853 Jeet memory cell  
A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect...
US20090052258 Systems, methods and devices for a memory having a buried select line  
Embodiments are described for programming and erasing a memory cell by utilizing a buried select line. A voltage potential may be generated between a source-drain region and the buried select line...

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