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US20150199177 RANDOM NUMBER GENERATOR BY SUPERPARAMAGNETISM  
In one general embodiment, a system includes at least one magnetic nanoparticle; a heating device for heating the at least one magnetic nanoparticle to induce a paramagnetic thermal instability in...
US20120127788 MRAM Cells and Circuit for Programming the Same  
A circuit includes magneto-resistive random access memory (MRAM) cell and a control circuit. The control circuit is electrically coupled to the MRAM cell, and includes a current source configured...
US20150042376 NONVOLATILE RESISTOR NETWORK ASSEMBLY AND NONVOLATILE LOGIC GATE WITH INCREASED FAULT TOLERANCE USING THE SAME  
Provided is a nonvolatile resistor network assembly characterized by that: it comprises a first and a second resistor network which are each composed of a plurality of nonvolatile resistive...
US20100321985 Boosted gate voltage programming for spin-torque MRAM array  
A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device...
US20130250662 TAMPER-RESISTANT MRAM UTILIZING CHEMICAL ALTERATION  
A magnetoresistive random access memory (MRAM) die may include an MRAM cell, a reservoir defined by the MRAM die, and a chemical disposed in the reservoir. At least one boundary of the reservoir...
US20120281464 Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate  
A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a...
US20130194862 NON-VOLATILE FLIP-FLOP  
A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current...
US20100309713 MAGNETIC RANDOM ACCESS MEMORY  
An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first...
US20110211388 HIGH GMR STRUCTURE WITH LOW DRIVE FIELDS  
Multi-period structures exhibiting giant magnetoresistance (GMR) are described in which the exchange coupling across the active interfaces of the structure is ferromagnetic.
US20120281460 NONCONTACT WRITING OF NANOMETER SCALE MAGNETIC BITS USING HEAT FLOW INDUCED SPIN TORQUE EFFECT  
A mechanism is provided for noncontact writing. Multiple magnetic islands are provided on a nonmagnetic layer. A reference layer is provided under the nonmagnetic layer. A spin-current is caused...
US20100309712 MAGNETIC RANDOM ACCESS MEMORY  
An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first...
US20140307499 BOOSTER CIRCUIT  
A booster circuit configured to boost a supplied voltage and provide a booster circuit output includes: an oscillator circuit configured to generate a clock signal; a charge pump circuit...
US20130329490 METHOD OF SWITCHING OUT-OF-PLANE MAGNETIC TUNNEL JUNCTION CELLS  
A method of switching the magnetization orientation of a ferromagnetic free layer of an out-of-plane magnetic tunnel junction cell, the method including: passing an AC switching current through...
US20140071741 OTP CELL WITH REVERSED MTJ CONNECTION  
A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming....
US20140153325 BODY VOLTAGE SENSING BASED SHORT PULSE READING CIRCUIT  
As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and...
US20120026784 RANDOM NUMBER GENERATOR  
According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element...
US20140254255 MRAM WTIH METAL GATE WRITE CONDUCTORS  
In one embodiment of the invention, there is provided a magnetic random access (MRAM) device. The device comprises a plurality of MRAM cells, wherein each MRAM cell comprises a magnetic bit, and...
US20130215672 MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE  
A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable...
US20140286085 POWER SUPPLY CIRCUIT AND PROTECTION CIRCUIT  
According to one embodiment, a power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp...
US20090073742 SEMICONDUCTOR STORAGE DEVICE AND OPERATING METHOD OF THE SAME  
A semiconductor storage device includes: reading blocks; third wirings; reading switches; a control circuit; and evaluating circuits. The reading blocks includes first and second wirings extended...
US20130176773 Reference Averaging for MRAM Sense Amplifiers  
A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising...
US20140071740 OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL  
A one time programming (OTP) apparatus unit cell includes multiple magnetic tunnel junctions (MTJs) and a shared access transistor coupled between the multiple MTJs and a fixed potential. Each of...
US20110051503 Magnetic Devices and Structures  
Magnetic devices, magnetoresistive structures, and methods and techniques associated with the magnetic devices and magnetoresistive structures are presented. For example, a magnetic device is...
US20150228322 NMOS-OFFSET CANCELING CURRENT-LATCHED SENSE AMPLIFIER  
A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit...
US20130258750 DUAL-CELL MTJ STRUCTURE WITH INDIVIDUAL ACCESS AND LOGICAL COMBINATION ABILITY  
A dual-cell spin-transfer torque random-access memory including a first magnetic tunneling junction and a second magnetic tunneling junction. An access circuit is coupled to the first and second...
US20130215673 MAGNETORESISTIVE LOGIC CELL AND METHOD OF USE  
A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable...
US20110280064 COMPOSITE RESISTANCE VARIABLE ELEMENT AND METHOD FOR MANUFACTURING THE SAME  
A composite resistance variable element includes a first resistance variable element in which a resistance value varies corresponding to a direction of inner magnetization, and a second resistance...
US20130070519 READ ARCHITECTURE FOR MRAM  
A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense...
US20130286721 LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP  
A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the...
US20150131369 PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ)  
A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the...
US20140269040 PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ)  
A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the...
US20110080773 CIRCUIT FOR GENERATING ADJUSTABLE TIMING SIGNALS FOR SENSING A SELF-REFERENCED MRAM CELL  
Controllable readout circuit for performing a self-referenced read operation on a memory device comprising a plurality of magnetic random access memory (MRAM) cells comprising a selecting device...
US20110075472 MAGNETORESISTIVE DEVICE HAVING SPECULAR SIDEWALL LAYERS  
A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall.
US20070296007 Shared ground contact isolation structure for high-density magneto-resistive RAM  
A buried ground contact that connects the ground electrodes of transistors in adjacent memory cells that are separated by an isolation region is described. In some embodiments, the buried ground...
US20120314489 SYSTEMS AND METHODS FOR DIRECT COMMUNICATION BETWEEN MAGNETIC TUNNEL JUNCTIONS  
Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output...
US20140126284 MRAM SENSING WITH MAGNETICALLY ANNEALED REFERENCE CELL  
Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising...
US20130016553 MRAM Sensing with Magnetically Annealed Reference Cell  
Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising...
US20090268512 MRAM with cross-tie magnetization configuration  
The incidence of half-select errors during MRAM programming has been significantly reduced by giving the free layer a shape that approximates an X so that, when the free layer switches, the...
US20100302838 Read disturb-free SMT reference cell scheme  
We describe a reference cell structure for determining data storing cell resistances in an SMT (spin moment transfer) MTJ (magnetic tunneling junction) MRAM array by comparing data cell currents...
US20110188298 MAGNETORESISTANCE ELEMENT, MRAM, AND INITIALIZATION METHOD FOR MAGNETORESISTANCE ELEMENT  
A magnetoresistance element is provided with: a magnetization recording layer that is a ferromagnetic layer. The magnetization recording layer includes: a magnetization reversal region having a...
US20100321976 Split Path Sensing Circuit  
A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path...
US20150213867 MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM  
Systems and methods are directed to multi-level cell (MLC) comprising: two or more programmable elements coupled to a common access transistor, wherein each one of the two or more programmable...
US20140071739 REFERENCE LEVEL ADJUSTMENT SCHEME  
A tunable reference cell scheme for magnetic random access memory (MRAM) circuitry selectively couples reference cells and data cells to shared write driver circuitry. Magnetic tunnel junctions...
US20100008131 MAGNETORESISTANCE EFFECT ELEMENT AND MRAM  
A magnetoresistance effect element according to the present invention comprises a magnetization tree layer 1 and a magnetization fixed layer 3 connected to the magnetization free layer 1 through a...
US20140269034 INTEGRATED CAPACITOR BASED POWER DISTRIBUTION  
An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same...
US20140010004 MAGNETIC MEMORY  
A magnetic memory includes: a base layer; a magnetization free layer; a barrier layer; and a magnetization reference layer. The magnetization free layer, with which the base layer is covered, has...
US20130155759 Test Structures, Methods of Manufacturing Thereof, Test Methods, and MRAM Arrays  
Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure...
US20090141542 MRAM DESIGN WITH LOCAL WRITE CONDUCTORS OF REDUCED CROSS-SECTIONAL AREA  
Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory...
US20120281463 MAGNETORESISTIVE EFFECT ELEMENT, AND MAGNETIC RANDOM ACCESS MEMORY  
A magnetoresistive effect element includes: a magnetization free layer having an invertible magnetization; an insulating layer being adjacent to the magnetization free layer; and a magnetization...
US20150036409 SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL USING MAGNETIC TUNNEL JUNCTION CELLS  
An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells.