Matches 1 - 35 out of 35


Match Document Document Title
US20080141207 Wiring Design System of Semiconductor Integrated Circuit, Semiconductor Integrated Circuit, and Wiring Design Program  
A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring...
US20080218235 SEMICONDUCTOR INTEGRATED CIRCUIT WITH FLIP-FLOP CIRCUITS MOUNTED THEREON  
A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop...
US20120139601 FLIP-FLOP CIRCUIT  
A flip-flop circuit includes an evaluation part connected to a first node and a second node to discharge the second node according to a voltage level of the first node, a conditional delay part...
US20150130524 LOW LEAKAGE RETENTION REGISTER TRAY  
A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention...
US20140253197 LOW LEAKAGE RETENTION REGISTER TRAY  
A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention...
US20140306745 FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION  
A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After...
US20140035645 SYSTEM AND METHOD TO PERFORM SCAN TESTING USING A PULSE LATCH WITH A BLOCKING GATE  
A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a...
US20150236676 REDUCED DYNAMIC POWER D FLIP-FLOP  
A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the...
US20140118046 STATE RETENTION POWER GATED CELL  
A state retention power gated (SRPG) cell includes an input control circuit having an input coupled to an input signal and an output. The input control circuit includes has transistors configured...
US20110274295 NEGATIVE-VOLTAGE CHARGE PUMP CIRCUIT  
A control unit alternately repeats a first state in which a first switch and a third switch are on and a second state in which a second switch and a fourth switch are on. A voltage detection unit...
US20090256609 LOW POWER FLIP FLOP THROUGH PARTIALLY GATED SLAVE CLOCK  
A system and method for reducing power consumption within a flip-flop circuit on a semiconductor chip. A gated input clock signal is received by a slave latch. The gated input clock is derived...
US20090085624 FLIP-FLOP CIRCUIT AND DUTY RATIO CORRECTION CIRCUIT USING THE SAME  
A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to...
US20110095800 FLIP-FLOP HAVING SHARED FEEDBACK AND METHOD OF OPERATION  
A method of operating a circuit includes receiving a first data signal at a first node. The first node is coupled to a second node to couple the first data signal to the second node. After...
US20080231336 SCAN FLIP-FLOP CIRCUIT WITH EXTRA HOLD TIME MARGIN  
The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation...
US20090108897 SEMICONDUCTOR DEVICE AND TIMING CONTROL METHOD FOR THE SAME  
A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal...
US20080224748 DIFFERENTIAL LATCH, DIFFERENTIAL FLIP-FLOP, LSI, DIFFERENTIAL LATCH CONFIGURATION METHOD, AND DIFFERENTIAL FLIP-FLOP CONFIGURATION METHOD  
A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is...
US20120013379 Charge-Injection Sense-Amp Logic  
A flip-flop circuit includes a charge injection module, a sense amp module, and a latch module. The charge injection module is configured to, in response to a clock signal, selectively provide...
US20080030250 FLIP-FLOP CIRCUIT  
A pair of transistors receive the input of signals of input data and the inverted input data. An activation circuit, which is provided between the pair of transistors and fixed potential,...
US20080238514 LEVEL-CONVERTED AND CLOCK-GATED LATCH AND SEQUENTIAL LOGIC CIRCUIT HAVING THE SAME  
A level-converted and clock-gated latch includes a pulse generator, a level converting unit, and a latch circuit. The pulse generator is provided with a first power-supply voltage and generates a...
US20080290921 Level converting flip-flop and method of operating the same  
A level converting flip-flop may include a data input circuit, a clocking circuit, a current mirror circuit, and/or a latch circuit. The data input circuit may be configured to generate a pull-up...
US20140306744 STATIC SIGNAL VALUE STORAGE CIRCUITRY USING A SINGLE CLOCK SIGNAL  
Signal value storage circuitry 2 is provided which includes a first transistor stack, a second transistor stack and a third transistor stack. The signal value storage circuitry is controlled by a...
US20090160517 FLIP-FLOP  
An apparatus comprises a first stage, a second stage, and a switch circuit. The first stage and the second stage are coupled between a first reference voltage and a second reference voltage. The...
US20120025886 SWITCH CONTROL DEVICE  
The present invention relates to a switch control device. The switch control device controls a switching operation of a power switch. The switch control device includes an auxiliary power device....
US20150077162 TRANSISTOR, CLOCKED INVERTER CIRCUIT, SEQUENTIAL CIRCUIT, AND SEMICONDUCTOR DEVICE INCLUDING SEQUENTIAL CIRCUIT  
A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor...
US20120019300 SHIFT REGISTER AND SEMICONDUCTOR DISPLAY DEVICE  
The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of...
US20100283524 SEMICONDUCTOR DEVICE  
A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a...
US20170126214 FLIP-FLOP CIRCUIT WITH DATA-DRIVEN CLOCK  
A flip-flop circuit includes a D flip-flop and a gating controller. The D flip-flop generates an output signal according to a data signal and a gated clock signal. The gating controller receives...
US20170070214 SEMICONDUCTOR CIRCUIT INCLUDING FLIP-FLOP  
A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level...
US20160365845 SEMICONDUCTOR CIRCUIT AND METHOD OF OPERATING THE CIRCUIT  
Provided is a semiconductor circuit which includes a first circuit configured to determine a voltage level of a feedback node based on a voltage level of input data, a voltage level of a latch...
US20160301396 Standby Mode State Retention Logic Circuits  
A retention mode sequential logic circuit has no balloon latch, and all its P-channel transistors are disposed in a single N-well. In one example, the circuit is a retention flip-flop that has an...
US20150102847 SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR SYSTEM  
An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the...
US20150003177 SEMICONDUCTOR DEVICE SUPPRESSING BTI DETERIORATION  
Disclosed herein is a device includes a command generation circuit that activates first and second command signals, an internal circuit that includes a plurality of transistors that are brought...
US20140312950 DATA HOLDING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A circuit including: an input stage that includes a first input unit into which input data is input and a pair of first output units and is driven by a first power-supply voltage; a pair of first...
US20140218081 SEMICONDUCTOR DEVICE AND CLOCK DATA RECOVERY SYSTEM INCLUDING THE SAME  
A semiconductor device includes a latch circuit. The latch circuit includes a sampling section that latches a differential input signal applied from a differential input node to the gates of a...
US20110148497 SEMICONDUCTOR DEVICE  
An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first...

Matches 1 - 35 out of 35