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US20140184296 MCML RETENTION FLIP-FLOP/LATCH FOR LOW POWER APPLICATIONS  
The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML...
US20150116019 APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS  
Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have...
US20140002161 CIRCUIT ARRANGEMENT, A RETENTION FLIP-FLOP, AND METHODS FOR OPERATING A CIRCUIT ARRANGEMENT AND A RETENTION FLIP-FLOP  
Various aspects of this disclosure provide a circuit arrangement, including: an input; a first latch circuit coupled to the input, the first latch circuit including a first forward inverter and a...
US20110148496 LEAKAGE CURRENT REDUCTION IN A SEQUENTIAL CIRCUIT  
A system and device for reducing leakage current in a sequential circuit is disclosed. In one embodiment, a system for reducing leakage current in a sequential circuit includes a combinational...
US20140253196 FLIP-FLOPS IN A MONOLITHIC THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) AND RELATED METHODS  
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed...
US20140269854 SYSTEMS AND METHODS FOR SERIAL COMMUNICATION  
This disclosure includes a point-to-point two-lineserial interface (TSI) suitable for use in a wireless communications device as well as in other applications. The TSI may employ a protocol...
US20130033295 CLOCK PHASE COMPENSATION FOR ADJUSTED VOLTAGE CIRCUITS  
Clock phases of clock signals in a dual clock tree are adjusted to compensate for variances in propagation delays of buffers in the clock tree. A first input clock and a second input clock are...
US20120280736 CIRCUIT AND METHOD FOR REDUCING THE PROPAGATION OF SINGLE EVENT TRANSIENT EFFECTS  
Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an...
US20120169392 MIN-TIME HARDENDED PULSE FLOP  
A flop circuit is disclosed. The flop circuit includes an input circuit configured to hold a logic value of an input signal received on its input node. The flop circuit further includes a storage...
US20130039666 Current-controlled CMOS logic family  
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic...
US20120229187 Storage circuitry and method with increased resilience to single event upsets  
Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at...
US20150194950 CIRCUIT FOR IMPROVING CLOCK RATES IN HIGH SPEED ELECTRONIC CIRCUITS USING FEEDBACK BASED FLIP-FLOPS  
A flip-flop circuit for enhancing clock rates in high speed electronic circuits, the flip-flop circuit having an input terminal, an output terminal, and a third terminal that controls the flow of...
US20080211558 Structure for Radiation Hardened Programmable Phase Frequency Divider Circuit  
A design structure embodied in a machine readable medium includes information for designing, manufacturing and/or testing a programmable phase frequency divider circuit implemented in CMOS...
US20130314138 STATE RETENTION SUPPLY VOLTAGE DISTRIBUTION USING CLOCK NETWORK SHIELDING  
An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low...
US20080218234 LOW POWER FLIP-FLOP CIRCUIT  
A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo...
US20100052756 LOW POWER AND SOFT ERROR HARDENED DUAL EDGE TRIGGERED FLIP FLOP  
A dual edge triggered flip flop can pass data values on a clock rising or falling edge. The dual edge triggered flip flop can be operated at half the clock speed of a single edge triggered flip...
US20130207705 SSPC DISTRIBUTION SYSTEM AND CONTROL STRATEGY  
A power distribution system includes the use of a master digital signal processor (DSP) and two slave DSPs connected to the master DSP. The slaves DSPs may be connected to each of a plurality of...
US20120182055 FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS  
A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second...
US20090267671 OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT  
Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be...
US20100060321 Clock control of state storage circuitry  
State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan...
US20150200651 MASTER-SLAVE FLIP-FLOP CIRCUIT AND METHOD OF OPERATING THE MASTER-SLAVE FLIP-FLOP CIRCUIT  
A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When...
US20090315603 DETECTION OF A DISTURBANCE IN THE STATE OF AN ELECTRONIC CIRCUIT FLIP-FLOP  
A method and a circuit for detecting a disturbance of a state of at least one first flip-flop from a group of several first flip-flops of an electronic circuit, wherein: the respective outputs of...
US20150061740 SCANNABLE FLOP WITH A SINGLE STORAGE ELEMENT  
In an embodiment, a flip flop circuit includes a master latch and a slave latch. The master latch comprises a storage element and at least two legs, including a data leg and at least one scan leg....
US20110018595 METASTABILITY HARDENED SYNCHRONIZER CIRCUIT  
A metastability hardened synchronizer circuit includes a plurality of transmission gates, each transmission gate responsive to an input signal and a clock signal to generate a driver signal. The...
US20130335129 Current Mode Logic Latch  
A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is...
US20080315932 PULSED STATE RETENTION POWER GATING FLIP-FLOP  
A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is...
US20110298516 Clock state independent retention master-slave flip-flop  
A master-slave flip-flop circuit is provided with a retention capability to support operation in both a normal mode and a retention mode. During the retention mode the retention circuitry drives...
US20130188428 APPARATUSES, CIRCUITS, AND METHODS FOR REDUCING METASTABILITY IN LATCHES  
Apparatuses, circuits, and methods are disclosed for reducing metastability in latches. In one such example apparatus, a circuit is configured to provide substantially complementary first and...
US20100141322 Non-Volatile State Retention Latch  
Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is...
US20090085626 Semiconductor integrated circuit and method for controlling semiconductor integrated circuit  
When a master circuit is in an inactive state, a slave circuit assigned to the master circuit is not used. Accordingly, the use efficiency of system recourses is decreased. To solve the above...
US20090039936 Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit  
Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A...
US20090267672 SERIAL PERIPHERAL INTERFACE (SPI) CIRCUIT AND DISPLAY USING THE SAME  
A serial peripheral interface (SPI) circuit and a display using the same are provided. The SPI circuit includes a mater device and a slave device. A serial data input pin and a serial data output...
US20090201063 DYNAMIC SEMICONDUCTOR DEVICE  
A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step...
US20080315912 Logic circuit including a plurality of master-slave flip-flop circuits  
According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input...
US20090309640 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING A MASTER-SLAVE FLIP-FLOP  
A semiconductor integrated circuit having a flip-flop with improve soft error resistance, including a controller which controls a clock signal generating circuit to output a first clock signal and...
US20100001774 Data retention flip flop for low power applications  
A disclosed embodiment is a data retention flip flop comprising master and slave circuits that are configured to be turned off when a single sleep mode signal is activated. The disclosed...
US20100007396 COMPOUND LOGIC FLIP-FLOP HAVING A PLURALITY OF INPUT STAGES  
A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the...
US20090128210 SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC CIRCUIT  
An electric circuit has a first differential circuit for transmitting input data to a first node, a second differential circuit for holding the first node data, a first clock transmission circuit...
US20140077854 SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN  
This disclosure relates generally to sequential state elements (SSEs). More specifically, embodiments of flip-flops are disclosed, along with computerized methods and systems of designing the...
US20120182056 LOW ENERGY FLIP-FLOPS  
Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state....
US20110298517 Master-slave flip-flop circuit  
A master-slave flip-flop circuit comprises a master stage for retaining a master signal, a slave stage for retaining a slave signal and a retention stage. During a normal mode of operation, the...
US20110234283 Scan/Scan Enable D Flip-Flop  
In accordance with an embodiment, an integrated circuit comprises a master-slave flip-flop, a selection logic circuit, and a pass structure. The selection logic circuit is configured to...
US20110260765 PHASE INTERLEAVING CONTROL METHOD FOR A MULTI-CHANNEL REGULATOR SYSTEM  
A multi-channel regulator system includes serially connected PWM integrated circuits, each of which determines a PWM signal for a respective channel to operate therewith, and individually controls...
US20090256608 Low leakage data retention flip flop  
A disclosed embodiment is a low leakage data retention flip flop comprising a master circuit for retaining data during sleep mode, wherein the master circuit is configured to receive a reduced...
US20080218233 Master-slave type flip-flop circuit and latch circuit  
A clock input circuit 13 receives power during standby mode and comprises a NAND circuit NAND0 that controls a clock signal CK using a standby mode signal RET. When the standby mode signal RET is...
US20080191769 SIGNAL TRANSMISSION CIRCUIT, SEMICONDUCTOR DEVICE THAT INCLUDES THE SIGNAL TRANSMISSION CIRCUIT, METHOD FOR DESIGNING THE SEMICONDUCTOR CIRCUIT DEVICE, AND CAD DEVICE  
A CAD device according to the embodiments includes means that determines signal transmission time of each signal transmission circuit in an LSI circuit, means that determines an output inversion...
US20090256596 FLIP-FLOP, FREQUENCY DIVIDER AND RF CIRCUIT HAVING THE SAME  
A flip-flop, and a frequency divider and an RF circuit using the flip-flop. The frequency divider, which receives a first signal and generates a second signal by dividing a frequency of the first...
US20130154708 CONFIGURABLE FLIP-FLOP  
A configurable flip-flop can be operated in a normal mode and a buffer mode. In the normal mode, the flip-flop latches data at the flip-flop input based on a clock signal. In the buffer mode, the...
US20090108896 Semiconductor Integrated Circuit Apparatus  
It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop...
US20090002044 Master-slave type flip-flop circuit  
A master-slave type flip-flop circuit consisting of a master latch and a slave latch, wherein the master latch comprises: a first clocked inverter to which data are input and a first latch circuit...

Matches 1 - 50 out of 128 1 2 3 >