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US20060170472 |
Variable delay circuit
A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay... |
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US20070069780 |
Delay cell of voltage controlled delay line using digital and analog control scheme
Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an... |
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US20070152723 |
Delay-locked loops for semiconductor devices and methods of controlling the same
A delay-locked loop (DLL) circuit capable of decreasing power consumption is provided. A DLL circuit includes a delay line, an output buffer, a replica circuit, a phase detector, a shift register... |
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US20120274376 |
DUTY CYCLE CORRECTOR CIRCUITS
Duty cycle corrector circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock... |
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US20140084977 |
Wide Frequency Range Delay Locked Loop
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a... |
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US20090153206 |
OPTICAL DRIVER INCLUDING A MULTIPHASE CLOCK GENERATOR HAVING A DELAY LOCKED LOOP (DLL), OPTIMIZED FOR GIGAHERTZ FREQUENCIES
An optical (disc) driving system including the DLL based multiphase clock generator circuit capable of generating 32 different phases from input clock having a frequency of 800 MHz or greater. The... |
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US20050093594 |
DELAY LOCKED LOOP PHASE BLENDER CIRCUIT
Techniques and circuit configurations for fine phase adjustments, for example, in a delay-locked loop (DLL) circuit are provided. Multiple phase signals may be generated from a single current... |
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US20130229214 |
SEMICONDUCTOR DEVICE GENERATING PHASE-CONTROLLED CLOCK SIGNAL
The semiconductor device includes a frequency detection circuit that outputs a frequency detection signal based on a frequency of a first clock signal; a phase comparison circuit that compares a... |
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US20160164529 |
FREQUENCY-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
A frequency-locked loop circuit includes a digital control oscillator that generates a clock, and an FLL (frequency-locked loop) controller that generates a frequency control code to control an... |
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US20080054963 |
DELAY LOCKED LOOP HAVING CHARGE PUMP GAIN INDEPENDENT OF OPERATING FREQUENCY
A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A charge pump is disclosed for providing a charge to a capacitive element on a voltage... |
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US20110001527 |
DUTY-CYCLE ERROR CORRECTION CIRCUIT
A duty cycle error correction circuit is disclosed. The circuit includes an inversion and delay circuit and a phase interpolator. The inversion and delay circuit is configured to receive an input... |
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US20100213991 |
DELAY-LOCKED LOOP CIRCUIT AND METHOD FOR SYNCHRONIZATION BY DELAY-LOCKED LOOP
A delay-locked loop circuit has an adjustment period setting module configured to set a rough adjustment period and a fine adjustment period, a delay time adjustment module configured to increase... |
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US20060214710 |
Delay-lock loop and method having high resolution and wide dynamic range
A delay-lock loop includes a phase detector comparing the phase of a digital input signal to the phase of a feedback signal. The phase detector generates a corresponding control signal that is... |
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US20070001724 |
DELAY LOCKED LOOP CIRCUIT
A delay locked loop circuit is disclosed. The circuit comprises a clock receiver for outputting an external clock, an inverted clock, which is an inverted version of the external clock, and a... |
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US20080157836 |
DELAY FIXING LOOP CIRCUIT FOR REDUCING SKEW BETWEEN EXTERNAL AND INTERNAL CLOCKS OR BETWEEN EXTERNAL CLOCK AND DATA, AND A CLOCK LOCKING METHOD THEREOF
The present invention relates to a delay fixing loop circuit including a delay fixing loop for reducing a skew between an external clock and a data, or between an external clock and an internal... |
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US20090167387 |
DELAY-LOCKED LOOP FOR TIMING CONTROL AND DELAY METHOD THEREOF
A delay-locked loop for timing control, includes a voltage-controlled delay line that delays a reference clock to generate a multi-phase clock comprising a plurality of delayed phase clocks; and... |
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US20150015310 |
CLOCK DELAY DETECTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME
Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period... |
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US20130271193 |
CIRCUITS AND METHODS TO GUARANTEE LOCK IN DELAY LOCKED LOOPS AND AVOID HARMONIC LOCKING
A delay locked loop (DLL) includes a phase detector (PD), a lock assistor (LA), a control voltage generator, and a voltage controlled delay line (VCDL). The PD determines a phase difference... |
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US20120187991 |
CLOCK STRETCHER FOR VOLTAGE DROOP MITIGATION
A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to... |
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US20110115569 |
SEMICONDUCTOR INTEGRATED CIRCUIT
The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock... |
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US20080211554 |
Time Delay Compensation Circuit Comprising Delay Cells Having Various Unit Time Delays
A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay... |
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US20100007390 |
Clock generating circuit, power converting system, and related method with spread spectrum for EMI reduction
A clock signal generating circuit includes a main delay circuit and a variable delay circuit. The main delay circuit receives a feedback clock signal, and outputs an output clock signal after a... |
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US20090027093 |
SAMPLING CIRCUIT AND METHOD
A sampling circuit for sampling an input data to obtain an output data includes a delay control unit, a first sampling unit, a second sampling unit, and a processing unit. The delay control unit... |
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US20090184741 |
Delay lock loop circuit, phase lock loop circuit, timing generator, semiconductor tester and semiconductor integrated circuit
A delay lock loop circuit and a phase lock loop circuit are designed to reduce a lock-up time, extend a lock range without increasing the number of bits of a counter, and quickly return to a lock... |
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US20110204942 |
CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME
A clock control circuit includes: a phase determination circuit that generates a phase determination signal based on a phase of an external clock signal; a counter circuit having a count value... |
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US20060197566 |
DLL circuit for providing an output signal with a desired phase shift
The present invention relates to a DLL circuit for providing an output signal which is shifted with by a desired phase shift with respect to a periodic input signal. In one embodiment, the DLL... |
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US20060232308 |
Delay stabilization circuit and semiconductor integrated circuit
A delay stabilization circuit capable of suppressing a drop in stability of delay or frequency and a cost increase and also able to shorten a design time, and a semiconductor integrated circuit... |
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US20150130521 |
METHOD, CIRCUIT AND SYSTEM FOR DETECTING A LOCKED STATE OF A CLOCK SYNCHRONIZATION CIRCUIT
Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a... |
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US20080315927 |
FREQUENCY ADJUSTING APPARATUS AND DLL CIRCUIT INCLUDING THE SAME
A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a... |
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US20110199138 |
Semiconductor device and test method thereof
A semiconductor device includes a PLL (Phase Locked Loop) circuit configured to generate a reception clock signal and a transmission clock signal based on a reference clock signal which has been... |
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US20080054957 |
Skew Correction Apparatus
A skew correction apparatus is composed of a variable delay line 200 for generating a delayed clock signal DCLK by delaying a clock signal CLK by a variable delay amount DT, a phase comparator 10... |
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US20080252341 |
CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME
A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a... |
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US20080265959 |
PLL circuit and frequency setting circuit employing the same
Disclosed is a PLL circuit in which an output signal of a frequency oscillator (VCO or ICO), an oscillation frequency of which is controlled by an electrical signal, is supplied via a high pass... |
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US20070279112 |
Semiconductor Memory
A semiconductor memory using a DLL circuit having a phase comparison circuit for comparing phases of an internal clock and a delay clock and a variable delay addition circuit for adjusting delay... |
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US20070279113 |
Dll Circuit
A DLL circuit comprises a dummy delay corresponding to an internal clock delay from an external clock, a variable delay addition circuit having a coarse and fine delay circuits adjusting delay... |
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US20060164141 |
Controlled delay line circuit with integrated transmission line reference
Embodiments of the present invention include a controlled delay line circuit comprising a feedback loop including an integrated transmission line, wherein the integrated transmission line is used... |
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US20070205817 |
Method, circuit and system for detecting a locked state of a clock synchronization circuit
Locked state detection circuits, devices, systems, and methods for detecting a locked or synchronized state of a clock synchronization circuit are described. Detection of a locked state includes a... |
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US20060038596 |
Delay locked loop circuitry and method for optimizing delay timing in mixed signal systems
A mixed signal system includes a digital circuit (17) clocked by a digital clock signal, an analog circuit (18) clocked by an analog clock signal, and clock generation circuitry (15) including a... |
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US20100118626 |
Delay device for shifting phase of strobe signal
A delay apparatus includes a DLL circuit including a delay element, the DLL circuit generating a first control signal for controlling the delay element in order that the delay element delays a... |
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US20110291717 |
SEMICONDUCTOR DEVICE
A semiconductor device includes a delay locked loop including a replica delay unit which is configured to delay a signal reflecting a delay amount of an output path of a signal, and a delay time... |
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US20090146705 |
DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN
A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register... |
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US20080150597 |
APPARATUS AND METHODS FOR CONTROLLING DELAY USING A DELAY UNIT AND A PHASE LOCKED LOOP
An apparatus for controlling a delay includes a phase locked loop and a delay unit. The phase locked loop generates an oscillation signal having a frequency substantially identical to that of a... |
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US20050242855 |
Delay locked loop circuit
Disclosed is a delay locked loop circuit (DLL) used for DDR SDRAM. The DLL provides a fast locking function. In particular, the DLL detects the level of a frequency and performs the fast locking... |
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US20090146704 |
DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN
A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input... |
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US20090072871 |
VARIABLE DELAY CIRCUIT, DELAY TIME CONTROL METHOD AND UNIT CIRCUIT
Variable delay circuit constructed by connecting plural unit circuits in series which can change a delay time from input of signal until output of the signal by increasing or decreasing the number... |
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US20140333357 |
CIRCUITS, APPARATUSES, AND METHODS FOR DELAY MODELS
Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a... |
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US20070273416 |
Signal delay loop and method for locking a signal delay loop
A signal delay loop (1) having a first signal delay line (4) which has a plurality of series-connectable signal delay elements with a respective associated component signal delay time (ΔTVE),... |
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US20060261870 |
Clock generation circuit
A clock generation circuit includes a phase comparator inputted with a reference clock and a feedback clock, a current controlled oscillator for generating a clock frequency according to an output... |
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US20060214709 |
Circuit arrangement for generating a synchronization signal
A circuit arrangement is provided for generating a synchronization signal having signal edge changes whose timings are defined. The arrangement includes a plurality of controllable signal delay... |
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US20060176091 |
Delay locked loop circuit
A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop... |