AcclaimIP-ad

Match Document Document Title
US20150213873 INJECTION-LOCKED PHASE LOCKED LOOP CIRCUITS USING DELAY LOCKED LOOPS  
An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a...
US20110221494 PHASE-LOCKED LOOP START UP CIRCUIT  
A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the...
US20110084742 DYNAMIC CURRENT SUPPLYING PUMP  
A pump system that can dynamically increase its current capability includes: a pump circuit, for producing an output voltage; an oscillator, for driving the pump circuit to pump at a particular...
US20110291715 PHASE ADJUSTMENT CIRCUIT  
In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first 1/2 frequency division circuit having a phase inversion function...
US20120200328 Reference Clock Compensation for Fractional-N Phase Lock Loops (PLLs)  
In one embodiment, a method includes determining a phase difference between a reference clock and a feedback clock in even and odd cycles for a phase lock loop (PLL). The even and odd cycles are...
US20130063192 PLL BANDWIDTH CORRECTION WITH OFFSET COMPENSATION  
A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is...
US20130120040 SYSTEM AND METHOD OF STABILIZING CHARGE PUMP NODE VOLTAGE LEVELS  
A method includes tracking a tuning voltage at a first circuit coupled to a first drain node of a first supply of a charge pump. The method also includes tracking the tuning voltage at a second...
US20090243673 PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP  
A PLL (phase locked loop) system includes a PLL and a lock detector. The PLL is for outputting a phase-locking clock signal. The lock detector is coupled to the PLL for detecting whether or not...
US20120062293 INJECTION-LOCKED PHASE-LOCKED LOOP WITH A SELF-ALIGNED INJECTION WINDOW  
An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of...
US20120051480 PHASE LOCKED LOOP, CDR CIRCUIT, AND RECEIVING CIRCUIT  
In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase...
US20120326795 VCO CALIBRATION SCHEME  
A technique to use a two-step calibration procedure to calibrate a voltage controlled oscillator (VCO) of a phase-locked loop. The first calibration step is an open-loop calibration procedure in...
US20110254601 LOCK DETECTOR, METHOD APPLICABLE THERETO, AND PHASE LOCK LOOP APPLYING THE SAME  
A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses,...
US20110227615 PLL WITH CONTINUOUS AND BANG-BANG FEEDBACK CONTROLS  
Phase locked loops (PLLs) are commonly employed in synthesizers, and there is ever increasing pressure to build PLLs that have better performance using low cost and low voltage digital...
US20120007644 COMPARATOR-BASED BUFFER WITH RESISTIVE ERROR CORRECTION  
A comparator-based buffer method and system enhance the driving capability of high-gain amplifiers with switched-capacitor loads. It includes a current source, a comparator, switches, sampling...
US20060139074 Charge pump DC / DC converter  
The present invention is a charge pump circuit provided as a charge pump DC/DC circuit for reducing the in-rush current in an initial operation of a charge pump operation. The charge pump DC/DC...
US20090167386 Charge pumping circuit, clock synchronization circuit having the charge pumping circuit, and method for operating the clock synchronization circuit  
A charge pumping circuit includes a first charge pump configured to perform a charge pumping operation on an output terminal in response to a first pumping control signal, an auxiliary charge...
US20150256063 CHARGE PUMP CIRCUIT  
A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and...
US20150061738 CHARGE PUMP CIRCUIT  
There is provided a charge pump circuit, including: a step-up circuit unit stepping up an input voltage at least once, according to a frequency and a voltage level of a clock signal; and a control...
US20140225652 CHARGE PUMP WITH A POWER-CONTROLLED CLOCK BUFFER TO REDUCE POWER CONSUMPTION AND OUTPUT VOLTAGE RIPPLE  
A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power...
US20130038365 Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer  
A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase...
US20090315599 CIRCUIT WITH A REGULATED CHARGE PUMP  
A circuit, method for regulation, and use thereof is provided, whereby the circuit can include a charge pump that is connected to a supply voltage terminal in order to produce a pump voltage from...
US20090309633 CHARGE PUMP FOR SWITCHED CAPACITOR CIRCUITS WITH SLEW-RATE CONTROL OF IN-RUSH CURRENT  
A ramp-up circuit for switched capacitor circuits with negative feedback to control the slew rate of in-rush current. Other embodiments are described and claimed.
US20140266343 AREA-EFFICIENT PLL WITH A LOW-NOISE LOW-POWER LOOP FILTER  
Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional...
US20120112809 METHOD AND DIGITAL CIRCUIT FOR GENERATING A WAVEFORM FROM STORED DIGITAL VALUES  
In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a...
US20120268179 VOLTAGE GENERATOR AND METHOD OF GENERATING VOLTAGE  
A voltage generator includes a clock generator configured to generate a first clock signal and a second clock signal having a longer cycle than the first clock signal, a pumping unit configured to...
US20110063002 BIAS CIRCUIT AND PHASE-LOCKED LOOP CIRCUIT USING THE SAME  
A bias circuit for generating an output bias current includes a first transistor, a passive component, a second transistor, and a bias current generator. The first transistor has a first node...
US20120051109 ACTIVE RECTIFIER WITH DELAY LOCKED LOOP, WIRELESS POWER RECEIVING APPARATUS INCLUDING ACTIVE RECTIFIER  
An active rectifier and a wireless power receiver including the active rectifier are provided. According to an aspect, an active rectifier may include: a first loop configured to provide voltage...
US20120068745 INJECTION-LOCKED FREQUENCY DIVIDER  
A representative injection-locked frequency divider includes a differential direct injection pair that is configured to receive and mix differential injection signals and an oscillator that is...
US20130049711 Frequency Lock Loop for Hysteretic Switching Regulators  
Embodiments of the present invention provide systems and methods for reducing switching frequency variation in a hysteretic switching regulator. Embodiments of the present invention provide a new...
US20120268178 Fully differential adaptive bandwidth PLL with differential supply regulation  
Provided is a fully differential adaptive bandwidth phase locked loop with differential supply regulation. One fully differential phase locked loop includes a differential active loop filter and...
US20140015577 PHASE LOCKED LOOP CIRCUIT WITH REDUCED JITTER  
A system and method for providing a phase-locked loop that reduces the effects of jitter caused by thermal noise of a resistor in a low-pass filter in the PLL. Thermal noise from various...
US20080164918 PLL LOOP BANDWIDTH CALIBRATION  
Systems and methodologies are described that facilitate calibration of the loop bandwidth of a phase-locked loop (PLL). Calibration for the loop bandwidth of a PLL as described herein can be...
US20080122505 Charge-pump circuit capable of regulating voltage without any external voltage regulator  
The present invention discloses a charge-pump circuit capable of regulating voltage without any external voltage regulator, wherein an input-modifying circuit is installed between the...
US20150170816 VARAINDUCTOR HAVING A SPIRAL INDUCTOR, VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE VARAINDUCTOR, AND PHASE LOCKED LOOP INCLUDING THE VARAINDUCTOR  
A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring...
US20140145768 CORRECTING FOR OFFSET-ERRORS IN A PLL/DLL  
The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect...
US20090174441 Peak Power Reduction Methods in Distributed Charge Pump Systems  
A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for...
US20150214892 FINFET VARACTOR  
The present disclosure relates to a FinFET varactor circuit having one or more control elements that control a relationship between capacitance and voltage of a FinFET MOS varactor without...
US20130120186 DELAY LOCKED LOOP  
A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first...
US20080129352 LINEAR PHASE FREQUENCY DETECTOR AND CHARGE PUMP FOR PHASE-LOCKED LOOP  
Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and...
US20090039929 Method to Reduce Static Phase Errors and Reference Spurs in Charge Pumps  
A phase-locked-loop (PLL) circuit, that includes: a differential phase-frequency detector, a charge pump and at least one logical gate disposed therebetween for providing cancellation of pulses of...
US20130285721 TIMING MONITOR FOR PLL  
Representative implementations of devices and techniques provide error detection for a phase-locked-loop (PLL) device. A timing monitor is arranged to count pulses output by one or more portions...
US20110121874 Systems and Methods for PLL Linearity Measurement, PLL Output Duty Cycle Measurement and Duty Cycle Correction  
Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One...
US20110248755 CROSS-FEEDBACK PHASE-LOCKED LOOP FOR DISTRIBUTED CLOCKING SYSTEMS  
According to various embodiments, a cross-feedback phase-locked loop (XF-PLL) may include a secondary phase/frequency detector to detect the phase/frequency differences between two adjacent...
US20100052771 CIRCUIT FOR DRIVING MULTIPLE CHARGE PUMPS  
A system for driving multiple charge pumps in a single unit is disclosed. The charge pump system includes a set of multiple charge pumps arranged in parallel. The charge pumps are connected to a...
US20110102033 LOW POWER CLOCKING SCHEME FOR A PIPELINED ADC  
Delay locked loops or DLLs are oftentimes employed in pipelined analog-to-digital converters (ADCs). Conventional DLLs, though, can consume an excessive amount of power. Here, a DLL is provided...
US20120182053 HALF CYCLE DELAY LOCKED LOOP  
An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also...
US20100085093 MULTI-PHASE CLOCK SYSTEM  
The invention relates to multi-phase clock system for receiving a plurality of clock signals (CLKo-n) comprising actual time events (aTE) defining different clock phases, the clock signals all...
US20090243674 Fractional-N Phased-Lock-Loop (PLL) System  
In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled...
US20120126866 Phase-Locked Loop with Calibration Function and Associated Calibration Method  
A phase-locked loop (PLL) includes a charge pump, a frequency divider, a voltage detector, a control module, and a calibration module. When a predetermined current amount and a predetermined...
US20080218229 ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY  
Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or...