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US20110102028 MULTIPHASE CLOCK GENERATION CIRCUIT  
The multiphase clock generation circuit includes a variable slew rate circuit and a phase interpolation circuit. In the variable slew rate circuit, the slew rate varies according to a first...
US20150168992 CONFIGURABLE CLOCK MESH CIRCUIT AND DEVICES INCLUDING THE SAME  
A clock mesh circuit includes a first clock circuit, a second clock circuit, and a switch circuit. The first clock circuit includes a first clock mesh network, and is configured to transmit a...
US20110298502 Switching Clock Sources  
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the...
US20140036963 CLOCK SYNCHRONIZATION FOR LINE DIFFERENTIAL PROTECTION  
A method and arrangement are provided for time synchronization between two geographically separated stationary clocks, such as first and second clocks located respectively at first and second ends...
US20110050300 Clock Generator  
A data processing system comprises a plurality of sub-circuits (10a, 10a, 10c), a clock generator (20) provided with a control circuit (22), a pool of oscillator circuits (24a, . . . 24f)...
US20080122501 CLOCK TIMING ADJUSTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT  
There is provided with a clock timing adjusting method for adjusting the difference of clock timings among a plurality of clock domains in a semiconductor integrated circuit which includes a clock...
US20090180335 INTEGRATED CIRCUIT WITH REDUCED POINTER UNCERTAINLY  
One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a...
US20130300466 SYSTEM AND METHOD FOR SYNCHRONIZING A LOCAL CLOCK WITH A REMOTE CLOCK  
A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a...
US20150123720 QUANTUM CLOCKS FOR A MASTER/SLAVE CLOCK ARCHITECTURE  
Embodiments of quantum clocks for a master/slave architecture are generally described herein. In some embodiments, a coupled pair of entangled particles is generated using a particle source. A...
US20080265955 SYNCHRONIZATION CIRCUIT AND METHOD  
An integrated circuit comprises a system clock and an interface clock. A synchronizing circuit is provided for synchronizing a control signal associated with a predetermined command, for example a...
US20090146700 DUTY RATIO CORRECTION CIRCUIT  
A duty ratio correction circuit including a reference clock generation block configured to generate first and second reference clocks that synchronize with rising and falling edges of an external...
US20140035635 APPARATUS FOR GLITCH-FREE CLOCK SWITCHING AND A METHOD THEREOF  
The invention relates to an apparatus and a method for glitch-free clock switching. In one embodiment this is accomplished by a first clock source, one or more second clock source and a clock...
US20120257463 DRIVER CIRCUIT  
A driver circuit includes pull-up and pull-down drivers driven by separate pre-drivers operating between different voltage rails. Data signals driving the pull-up driver and the pull-down driver...
US20090231001 Signal recovery circuit  
A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals...
US20110286400 METHOD FOR SENDING AND RECEIVING CLOCK, APPARATUS FOR TRANSMITTING CLOCK  
A method for sending and receiving a clock and an apparatus for transmitting the clock. Several kinds of clocks are encoded and framed at a sending port so that the clocks needed by all modes of...
US20110163785 SIMPLE INTERLEAVED PHASE SHIFT CLOCK SYNCHRONIZATION FOR MASTER/SLAVE SCHEME  
An apparatus for interleaved phase shift clock synchronization includes a master clock generator and at least one slave clock generator. The master clock generator provides a ramp signal or reset...
US20120229184 All Digital Serial Link Receiver with Low Jitter Clock Regeneration and Method Thereof  
An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference...
US20130049827 SYNCHRONIZING GLOBAL CLOCKS IN 3D STACKS OF INTEGRATED CIRCUITS BY SHORTING THE CLOCK NETWORK  
There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution...
US20130207698 CLOCK DISTRIBUTION SYSTEM AND METHOD FOR A MULTI-BIT LATCH  
A clock distribution system for a multi-bit latch. The clock distribution system may include a plurality of branches, each connected to a common clock input. Each branch may be driven by an input...
US20090128199 BIASED CLOCK GENERATOR  
A method and system for generating a pair of synchronized clock signals is described. The system includes a first device connected between a first output voltage and an input reference voltage,...
US20080074151 DUAL-EDGE-TRIGGERED, CLOCK-GATED LOGIC CIRCUIT AND METHOD  
A dual-edge-triggered clock-gated logic circuit includes; a delay clock generator operating to generate first, second, third and fourth delay clock signals in response to a clock signal, and a...
US20100289538 CLOCK CONDITIONING CIRCUIT  
A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts...
US20090058476 RECEIVER CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED CIRCUIT  
A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to...
US20110221485 Time synchronization method and apparatus  
The present invention discloses a time synchronization method and apparatus. The method comprises: each net element node locks a clock synchronization signal of its upper-level net element node...
US20100073043 NETWORK AND METHOD FOR SETTING A TIME-BASE OF A NODE IN THE NETWORK  
A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronisation system connected to...
US20100117692 MULTI-PHASE CLOCK GENERATION CIRCUIT HAVING A LOW SKEW IMPRECISION  
A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation...
US20100052743 SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD  
The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit...
US20140281652 DATA SYNCHRONIZATION ACROSS ASYNCHRONOUS BOUNDARIES USING SELECTABLE SYNCHRONIZERS TO MINIMIZE LATENCY  
A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first...
US20090121756 PSEUDO-SYNCHRONOUS SMALL REGISTER DESIGNS WITH VERY LOW POWER CONSUMPTION AND METHODS TO IMPLEMENT  
Methods and apparatus for implementing and operating one or more pseudo-synchronous registers with reduced power consumption, and reduced complexity for transferring data between clock domains....
US20110128052 CLOCK HAND-OFF CIRCUIT  
A second latch latches the output data of a first latch using a third clock having the same frequency as that of a first clock. A third latch latches the output data of the second latch using a...
US20110080393 Driver and organic light emitting diode display using the same  
A driver comprises odd-numbered stages configured to be driven by first and second clock signals and even-numbered stages configured to be driven by the second and third clock signals. Each stage...
US20140203850 POWER MANAGED SYNCHRONIZERS FOR ASYNCHRONOUS INPUT SIGNALS  
Clock-gated synchronizer circuitry includes a number of clock-gated synchronizers, with each clock-gated synchronizer configured to synchronize an asynchronous input signal into a clock domain....
US20090140781 CIRCUIT FOR DATA SYNCHRONIZATION OF I2C TIME CONTROLLER IN DISPLAY DEVICE AND METHOD THEREOF  
A method of controlling an interface between an I2C master in a time controller for a liquid crystal display and an external memory may include causing a pre-scaler to determine whether or not a...
US20140292385 INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION IN A TEST MODE, AND RELATED METHODS  
An integrated circuit includes an N number of functional logic blocks, with N being greater than or equal to two, and clock staggering test circuitry. When the clock staggering test circuitry is...
US20130002298 Signal value storage circuitry with transition detector  
A D-type flip-flop 2 includes tristate inverter circuitry 4, 6 passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate 10 to...
US20100019811 Self-Stabilizing Byzantine-Fault-Tolerant Clock Synchronization System and Method  
Systems and methods for rapid Byzantine-fault-tolerant self-stabilizing clock synchronization are provided. The systems and methods are based on a protocol comprising a state machine and a set of...
US20110068839 SYSTEM EMPLOYING SYNCHRONIZED CRYSTAL OSCILLATOR-BASED CLOCK, TO BE USED IN EITHER DISCRETE OR INTEGRATED APPLICATIONS  
A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in...
US20090261872 FAST, LOW POWER FORMATTER FOR AUTOMATIC TEST SYSTEM  
Automated test equipment (ATE) used to test semiconductor components during the manufacturing process. The ATE generates and measures signals at test points of a device under test. The ATE...
US20090160507 Apparatus and method for clock signal synchronization in JTAG testing in systems having selectable modules processing data signals at different rates  
In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application...
US20080290914 Self-Clearing Asynchronous Interrupt Edge Detect Latching Register  
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first...
US20140210524 USING HIGH FREQUENCY CRYSTAL FROM EXTERNAL MODULE TO TRIM REAL TIME CLOCK  
Techniques including methods and apparatus for calibrating a local clock are provided in an implantable medical device. The implantable medical device includes a telemetry module for receiving a...
US20090128200 RECEIVER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS  
A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural...
US20090031053 SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE WITH THE SAME  
An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet...
US20090237129 SEMICONDUCTOR DEVICE AND DATA PROCESSOR  
Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while...
US20070257716 Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults  
The present invention relates to a test system (100) interposed between a clock monitor self-timed memory. In an example embodiment, the test system (100) receives an internal clock signal (104)...
US20100271086 DUAL-BAND COUPLED VCO  
In a dual band capable voltage controlled oscillator VCO circuit comprising two voltage controlled oscillator units VCO1, VCO2, the voltage controlled oscillator units VCO1, VCO2 are synchronized...
US20110309865 PARALLEL SYNCHRONIZING CELL WITH IMPROVED MEAN TIME BETWEEN FAILURES  
In some embodiments, a synchronizing circuit includes at least one synchronization device that operates at a lower clock frequency than another synchronization device in the synchronization...
US20100001769 Method and Apparatus for Synchronizing Time Stamps  
Various apparatuses and methods for synchronizing time stamps are disclosed herein. For example, some embodiments of the present invention provide apparatuses for synchronizing a coarse time stamp...
US20090045853 TIMING CONTROLLER, DISPLAY APPARATUS HAVING THE SAME AND METHOD FOR DRIVING THE DISPLAY APPARATUS  
A timing controller, a display apparatus having the timing controller and a method for driving the display apparatus, the timing controller includes a control part, an inner clock and a control...
US20130222021 TRANSMITTING APPARATUS AND TRANSMITTING METHOD  
A transmitting apparatus includes a first circuit to which a base clock and a first clock condition are input, the first circuit outputting a first enable signal based on the base clock and the...

Matches 1 - 50 out of 79 1 2 >