Matches 1 - 31 out of 31


Match Document Document Title
US20140292374 METHOD FOR CONTROLLING AN INTEGRATED CIRCUIT  
A method for controlling an IC having logic cells and a clock-tree cell. Each logic cell has first and second FETs, which are pMOS and nMOS respectively. The clock-tree cell includes third and...
US20110032000 ULTRA-LOW POWER MULTI-THRESHOLD ASYNCHRONOUS CIRCUIT DESIGN  
A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction....
US20140225645 CLOCK BUFFER  
A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has...
US20110267107 CIRCUIT FOR REDUCING NEGATIVE BIAS TEMPERATURE INSTABILITY  
A circuit includes an operational PMOS transistor of a logic gate driver. A control circuit is configured to turn off the operational PMOS transistor during a standby mode. The circuit also...
US20100073029 Complementary Energy Path Adiabatic Logic  
A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and...
US20070176642 Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage  
Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology...
US20120139584 DOMINO LOGIC CIRCUITS AND PIPELINED DOMINO LOGIC CIRCUITS  
A domino logic circuit includes a first evaluation unit, a second evaluation unit and an output unit. The first evaluation unit precharges a first dynamic node, discharges a footer node in a first...
US20130038350 SINGLE-TO-DIFFERENTIAL CONVERSION CIRCUIT AND METHOD  
A conversion circuit includes a first inverter having an input node configured to receive a single-ended signal and second and third inverters each having respective inputs coupled to an output of...
US20130257480 CLOCK-DELAYED DOMINO LOGIC CIRCUIT AND DEVICES INCLUDING THE SAME  
A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit...
US20090146734 Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) Circuits  
In one embodiment, a circuit includes a first circuit block connected to ground via a first sleep transistor, a first virtual ground node between the first circuit block and the first sleep...
US20150162910 LOW-POWER INTERNAL CLOCK GATED CELL AND METHOD  
A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at...
US20090230994 DOMINO LOGIC CIRCUIT AND PIPELINED DOMINO LOGIC CIRCUIT  
A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level...
US20130246834 PSEUDO-STATIC DOMINO LOGIC CIRCUIT AND APPARATUSES INCLUDING SAME  
A domino logic circuit includes a plurality of domino logic stages connected in series between a latch and a flip-flop and a clock signal generator generating a clock signal having a first duty...
US20140070847 CLOCK GATING LATCH, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT EMPLOYING THE SAME  
A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a...
US20100073030 Adaptive Keeper Circuit to Control Domino Logic Dynamic Circuits Using Rate Sensing Technique  
The present invention provides an adaptive keeper circuit to control Domino Logic Dynamic Circuits using Rate Sensing Technique to provide reduced contention and efficient process tracking at...
US20110193588 MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE MULTI-MODE CIRCUIT  
Multi-mode circuit (the circuit) and a method for preventing degradation in the circuit. The circuit includes a first transistor that enables functioning of the circuit in a first mode. The first...
US20070024322 Leakage current reduction scheme for domino circuits  
A method and system for leakage current reduction in domino circuits is described. The system includes a domino circuit with a dynamic gate, a static gate, and a standby signal to set the domino...
US20050212562 Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone  
An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of...
US20080048725 Domino Circuit with Master and Slave (DUAL) Pull Down Paths  
A domino circuit and method include a master evaluation node to which a master discharge path with a wide input AND gate is coupled and a virtual evaluation node to which an output stage and slave...
US20060202719 Semiconductor integrated circuit device and design method thereof  
In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in...
US20120299622 Internal Clock Gating Apparatus  
An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino...
US20150070050 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE  
A semiconductor integrated circuit device includes a first flip-flop circuit receiving data in synchronization with a first clock signal, a logic circuit performing a predetermined process on data...
US20090167358 FULLY INTERRUPTIBLE DOMINO LATCH  
A domino latch is provided that comprises a forward path circuit and a feedback path circuit. The feedback path includes a plurality of keeper transistors, an inverter, and at least one interrupt...
US20130246819 FOOTER-LESS NP DOMINO LOGIC CIRCUIT AND RELATED APPARATUS  
A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in...
US20150244367 Method and Apparatus for Equalizing a Level Shifted Signal  
A method and apparatus are provided for equalizing an output of a level shifter so as to obtain a symmetrical transition. In one implementation, a transition equalizing inverter includes: an NMOS...
US20120287712 SEMICONDUCTOR DEVICE  
A semiconductor device including a logic circuit capable of decreasing a leakage current occurred during a standby state is provided. The semiconductor device includes a power supply portion for...
US20130147518 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE  
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential...
US20110102018 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE  
In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential...
US20100315126 DYNAMIC CIRCUIT WITH SLOW MUX INPUT  
A logic circuit includes a control circuit including a first logic gate to receive a selection signal and a first input signal and to output a pulse control signal and a second logic gate to...
US20160352311 SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE  
A semiconductor device includes a logic circuit capable of storing configuration data. The logic circuit includes a latch circuit, an arithmetic circuit, a delay circuit, and a first output timing...
US20150280710 CLOCK TREE UNIT CELL CIRCUIT, CLOCK TREE, AND APPARATUS  
A clock tree unit cell circuit includes a first input terminal configured to receive a clock signal from an upstream side of a clock tree; a first output terminal configured to output a clock...

Matches 1 - 31 out of 31