Matches 1 - 14 out of 14


Match Document Document Title
US20130015884 SWITCHING CIRCUITS, LATCHES AND METHODS  
Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching...
US20110193593 Apparatus for Metastability-Hardened Storage Circuits and Associated Methods  
A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of...
US20110074466 APPARATUS FOR METASTABILITY-HARDENED STORAGE CIRCUITS AND ASSOCIATED METHODS  
A metastability-hardened storage circuit includes at least one inverting circuit. The inverting circuit has a logical input. The logical input of the inverting circuit is split into a pair of...
US20090121745 DFLOP CIRCUIT FOR AN EXTERNALLY ASYNCHRONOUS-INTERNALLY CLOCKED SYSTEM  
A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and...
US20080074151 DUAL-EDGE-TRIGGERED, CLOCK-GATED LOGIC CIRCUIT AND METHOD  
A dual-edge-triggered clock-gated logic circuit includes; a delay clock generator operating to generate first, second, third and fourth delay clock signals in response to a clock signal, and a...
US20150214933 METASTABILITY GLITCH DETECTION  
This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample...
US20150015305 DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY  
Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified...
US20110199121 SMART EDGE DETECTOR  
In some embodiments related to a smart edge detector, the smart edge detector uses a second clock in a receiver domain (e.g., clock CLK_D2) to trigger a first flip-flop having a first clock in a...
US20100194436 VERIFICATION SUPPORT SYSTEM AND METHOD  
A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a...
US20170141764 METASTABILITY GLITCH DETECTION  
This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample...
US20150326210 TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE  
An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and...
US20150138905 Low Leakage State Retention Synchronizer  
Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a...
US20150102838 SEMICONDUCTOR DEVICE AND METHOD FOR DETECTING STATE OF INPUT SIGNAL OF SEMICONDUCTOR DEVICE  
A semiconductor device includes a signal detection unit suitable for detecting a state of an input signal and generating a detection signal based on a detected result, and a signal transmission...
US20140347099 APPARATUSES, CIRCUITS, AND METHODS FOR REDUCING METASTABILITY IN DATA SYNCHRONIZATION  
Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resin ling from metastability in data synchronization. In one such example apparatus, a sampling...

Matches 1 - 14 out of 14