Applications in Class 326/93

Matches 1 - 29 out of 29

Match	Document	Document Title
1	US20050060676	Semiconductor integrated circuit and method for designing same The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included...
2	US20070008011	Distributed power and clock management in a computerized system A computer circuit includes a plurality of digital logic circuits, each having a locally regulated voltage supply and a clock. The clock and locally regulated voltage supply of each of the...
3	US20100001762	DOMAIN CROSSING CIRCUIT AND METHOD A domain crossing circuit for reducing current consumption includes an internal counter to count an internal clock in response to the release of a reset signal, outputting an internal code, a...
4	US20110285421	SYNCHRONOUS LOGIC SYSTEM SECURED AGAINST SIDE-CHANNEL ATTACK An improvement in the security of a logic system from attacks that observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the...
5	US20110299346	APPARATUS FOR SOURCE-SYNCHRONOUS INFORMATION TRANSFER AND ASSOCIATED METHODS An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The...
6	US20130181742	METHOD AND APPARATUS TO SERIALIZE PARALLEL DATA INPUT VALUES A method includes applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple...
7	US20070146011	Duty cycle adjustment Disclosed herein are duty cycle adjustment circuits to control the duty cycle in a clock signal. In some embodiments, a circuit is provided comprising a clock driver to drive a differential clock...
8	US20110099407	Apparatus for High Speed Data Multiplexing in a Processor A processer, for example a field programmable gate array (FPGA), comprises input/output (I/O) logic including timing adjustment logic operative to synchronize a time division multiplexed (TDM)...
9	US20080028343	SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME A semiconductor integrated circuit comprising: a clock gating cell to which an enable signal and a clock signal are input, so as to output a gated clock signal generated by output-controlling said...
10	US20080204080	Mobile circuit robust against input voltage change An inverting flip-flop (F/F) circuit type monostable-bistable transition logic element (MOBILE) circuit that uses resonant tunneling diodes (RTDs) and can prevent a malfunction caused by low...
11	US20130086444	ERROR DETECTION CODE ENHANCED SELF-TIMED/ASYNCHRONOUS NANOELECTRONIC CIRCUITS Provided is a system including a group of error-detecting/correcting-code self-checked/self-timed/self-corrected circuits for logic robust and performance scalable nanoelectronic design,...
12	US20100244901	CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS A clock switching circuit includes: a selector that selects one of a plurality of clocks based on a select signal and outputs the clock selected as a selected clock; a mask circuit that masks the...
13	US20100079168	SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD A semiconductor integrated circuit has a scan chain with a scan clock signal line for clocking scan flip-flops and a scan test signal line for transferring scanning data into and out of the scan...
14	US20070018688	Digital Logic Unit The invention provides a digital logic driven by a master clock signal and includes logic circuitry with processing stages capable of performing logic operations within a fraction of the period of...
15	US20090212818	Integrated circuit design method for improved testability An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a...
16	US20050040856	Domino circuitry compatible static latch A circuit provides latched data in a domino circuit environment. The circuit receives a pair of input signals that are either in complementary logic states, which is data, or in the same logic...
17	US20150341032	LOCALLY ASYNCHRONOUS LOGIC CIRCUIT AND METHOD THEREFOR A locally asynchronous logic circuit includes an input latch; a synchronous-to-asynchronous control circuit having an input for receiving a first clock signal, a first output coupled to the latch...
18	US20070247195	LOW OUTPUT-TO-OUTPUT SKEW/LOW JITTER STAGGERED OUTPUT BUFFER A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The...
19	US20060044016	Integrated circuit with signal skew adjusting cell selected from cell library An integrated circuit comprises digital circuitry having at least one digital logic cell and at least one skew adjusting cell. The skew adjusting cell is configured to adjust the skew of a signal...
20	US20080066043	METHOD AND SYSTEM FOR CLOCK TREE GENERATION A method for generating a clock tree between a clock source and a plurality of logic units is disclosed. The logic units are defined to operate according to a clock signal generated from the clock...
21	US20080054945	Method and apparatus for loss-of-clock detection Methods and apparatus are provided for loss-of-clock detection. A loss of a clock signal is detected by delaying the clock signal using one or more delay elements; and applying an output of the...
22	US20120032703	PULSE-SHRINKING DELAY LINE BASED ON FEED FORWARD A shrinking-pulse digital delay line (400) has a cascade of a plurality of stages (102,104) for modifying a width of a pulse propagating down the cascade (106 to 118). Each specific one of the...
23	US20080309373	INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT An integrated circuit device includes a clock signal supply control circuit that controls a timing when a master clock signal output from an oscillation circuit is supplied to an internal circuit...
24	US20130002297	BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the...
25	US20120068736	DESIGN APPARATUS, DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT A design apparatus according to the present embodiment includes a scheduling section, a group ID assigning section, a transition violation detecting section and a state inserting section. The...
26	US20090108875	Structure for a Limited Switch Dynamic Logic Cell Based Register A design structure for a circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of...
27	US20080297207	DOUBLE DATA RATE TRANSMITTER AND CLOCK CONVERTER CIRCUIT THEREOF A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit...
28	US20070229115	Method and apparatus for correcting duty cycle error in a clock distribution network A clock distribution network for distributing a repetitive timing signal throughout an integrated circuit, the timing signal being within a range of frequencies about a first frequency, includes...
29	US20090002032	DATA SYNCHRONIZER A data synchronizer is to avoid the pulse width constraint on the data while synchronizing the data between two devices operating at different clock rates. The data synchronizer may comprise one...

Matches 1 - 29 out of 29