Matches 1 - 27 out of 27


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US20110012640 CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS  
Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.
US20090153188 PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE)  
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes...
US20160087635 Operational Time Extension  
Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The...
US20090144485 PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPS) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAS, DPGAS, AND THE LIKE)  
In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes...
US20080164936 Apparatus and Methods for Adjusting Performance of Programmable Logic Devices  
A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is...
US20080024163 PROGRAMMABLE LOGIC DEVICE  
Provided is a programmable logic device which increases the speed of switching the functions of a reconfigurable core by high-speed configuration data transfer. The programmable logic device...
US20080191739 Method and apparatus for universal program controlled bus architecture  
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit...
US20090033359 Programmable logic device with millimeter wave interface and method for use therewith  
A programmable logic device includes at least one input port, at least one output port, a plurality of configurable blocks and a program interface module coupled to configure the plurality of...
US20060190908 Coding of FPGA and standard cell logic in a tiling structure  
A method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer...
US20110099407 Apparatus for High Speed Data Multiplexing in a Processor  
A processer, for example a field programmable gate array (FPGA), comprises input/output (I/O) logic including timing adjustment logic operative to synchronize a time division multiplexed (TDM)...
US20080218206 FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK  
A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a...
US20050248365 Distributive computing subsystem of generic IC parts  
A PCB subsystem of IC parts is proposed. The PCB assembly contains single or plural of chips, each contains Giga Byte storage and 10 k gate equivalent Schottky CMOS (SCMOS) based field...
US20060097750 Electronic circuit with array of programmable logic cells  
An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a random logic...
US20120161813 SWITCH APPARATUS FOR FIELD PROGRAMMABLE GATE ARRAY  
A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration...
US20100287336 EXTERNAL I/O SIGNAL AND DRAM REFRESH SIGNAL SYNCHRONIZATION METHOD AND ITS CIRCUIT  
In an LSI that determines timing of DRAM refresh by a refresh timer to synchronize an external I/O signal and DRAM refresh timing with each other, a circuit configuration capable of controlling a...
US20100213976 Hierarchical FPGA configuration  
A system for configuring programmable logic devices includes a serial data bus, a first device to fan-out data signals on the serial data bus, a second device to fan-in data signals on the serial...
US20080180129 FPGA ARCHITECTURE WITH THRESHOLD VOLTAGE COMPENSATION AND REDUCED LEAKAGE  
A method for providing transistor threshold voltage compensation in an FPGA integrated circuit with a plurality of programmable circuit blocks includes measuring the effective transistor threshold...
US20110204918 DELAY SIMULATION SYSTEM, DELAY SIMULATION METHOD, PLD MAPPING SYSTEM, PLD MAPPING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT  
A delay simulation system comprises an input unit configured to input a netlist, a library, and information including load capacitances; and a simulation unit; the library defines a plurality of...
US20100162017 SYSTEMS AND METHODS FOR IMPLEMENTING STANDBY FUNCTIONALITY USING FIELD PROGRAMMABLE GATE ARRAYS  
The disclosed embodiments relate to an electronic device comprising a logic circuit comprising a plurality of logic banks. In accordance with embodiments of the present technique, at least one of...
US20090302887 APPARATUS FOR POWER CONSUMPTION REDUCTION IN PROGRAMMABLE LOGIC DEVICES AND ASSOCIATED METHODS  
A programmable logic device (PLD) includes a driver circuit, a configuration memory, and a control circuit. The configuration memory stores driver strength information for the driver circuit. The...
US20170054444 RESOLUTION TIMING  
A system for improving signal timing measurement resolution for an asynchronous measurement signal, the system being adapted to produce multiple phase shifted timing outputs, each having a fixed...
US20090256589 PROGRAMMABLE DEVICE, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING PROGRAMMABLE DEVICE  
A programmable device connected to a storage unit which stores logic circuit configuration information to form a logic circuit and control circuit configuration information to form a control...
US20110148461 METHOD AND DEVICE FOR GENERATING AND SUPPLYING CONFIGURATION DATA FOR AND/OR TO A PROGRAMMABLE, INTEGRATED LOGIC CIRCUIT  
In a method for the supply of encoded configuration data (14) to a programmable, integrated logic circuit (4), un-encoded configuration data (12) comprising an algorithm (20) are initially...
US20120081147 APPARATUS AND METHOD FOR CONTROLLING SIGNAL DISTRIBUTION IN A SEMICONDUCTOR INTEGRATED CIRCUIT  
A programmable logic device includes a plurality of first type repeating units, each of which includes interconnecting lines and a logic block comprising logic circuits. The plurality of first...
US20090198759 Circuits for computational set theory  
The present invention provides a set of analog circuit modules and procedures for assembling them into circuits that represent fundamental expressions and operations in mathematics, and more...
US20100156462 PROGRAMMABLE LOGIC ARRAY AND PROGRAMMABLE LOGIC ARRAY MODULE GENERATOR  
A PLA contains an input plane (10) including a plurality of data lines (103) and a plurality of product term lines (104) having voltage levels changed in accordance with signal input to the...
US20090045839 ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE  
A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare...

Matches 1 - 27 out of 27