Matches 1 - 20 out of 20


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US20070106965 Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same  
Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting...
US20080079461 INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL  
An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over...
US20050138593 Semiconductor integrated circuit having diagonal wires, semiconductor integrated circuit layout method, and semiconductor integrated circuit layout design program  
A semiconductor integrated circuit includes a plurality of first wires running in a first direction of 0°, a 45° diagonal, a 90° angle and a 135° diagonal in a subject area disposed in a...
US20070157146 METHOD OF PACKING-BASED MACRO PLACEMENT AND SEMICONDUCTOR CHIP USING THE SAME  
A multi-packing tree (MPT) macro placer. The MPT macro placer comprises reading input files in a LEF/DEF format, creating a k-level binary multi-packing tree comprising k branch nodes each...
US20140167818 Method and System for Multiple I/O Regions  
Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available...
US20060044018 Variable threshold transistor for the Schottky FPGA and multilevel storage cell flash arrays  
An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode...
US20090184733 LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL  
This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors....
US20080036503 VARIABLE THRESHOLD TRANSISTOR FOR THE SCHOTTKY FPGA AND MULTILEVEL STORAGE CELL FLASH ARRAYS  
An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode...
US20080180132 Semiconductor device and method of fabricating the same  
This invention efficiently suppresses the power noise of an LSI. A semiconductor device includes first and second interconnection layers. The first interconnection layer has a source voltage...
US20060119392 Semiconductor integrated circuit and layout design method thereof, and standard cell  
A semiconductor integrated circuit comprises: a first standard cell which includes a first logic circuit and a first switch for controlling current supply to the first logic circuit; and a second...
US20120194217 INPUT/OUTPUT CORE DESIGN AND METHOD OF MANUFACTURE THEREFOR  
One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary...
US20070182456 Reducing Pin Count When the Digital Output is to be Provided in Differential or Single-ended Form  
An integrated circuit provides digital output signals in either single-ended or differential form on a shared set of pins. A control circuit generates signals to ensure that when one form...
US20100079168 SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD  
A semiconductor integrated circuit has a scan chain with a scan clock signal line for clocking scan flip-flops and a scan test signal line for transferring scanning data into and out of the scan...
US20060261856 Semiconductor chip and semiconductor device incorporating the same  
A semiconductor chip is composed of first and second pads receiving first and second input signals, respectively, a logic circuit, and a circuit block connected to an output of the logic circuit....
US20070018691 Multi-pad structure for semiconductor device  
A pad layout structure may include a pad and adjacent circuit areas having an electrostatic protection circuit and a data input/output circuit. The pad may be selectively connected to the adjacent...
US20110025378 SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD THEREOF  
A layout method for a semiconductor integrated circuit includes, generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic...
US20060261859 Semiconductor integrated circuit device  
The purpose of the invention is providing a semiconductor circuit being able to supply either “L” level signal or “H” level signal to the subsequent stage logic circuit thereof. The latch circuit...
US20060214696 Voltage supply structure and method  
FIG. 1c shows a logic tree 10c comprising a plurality of logic paths (27, 29, 31, 33) connected at a root 11c. The length of each path represents the delay of the path at a nominal supply voltage....
US20050253627 Multi level fixed parameter assignment  
A method for assigning a value to a fixed parameter in an electrical device where the fixed parameter has three or more states includes associating a voltage value to each of the states of the...
US20070106964 Optimized microchip and related methods  
Various embodiments of an optimized microchip and methods of fabricating and operating the same are provided. One microchip embodiment, among others, comprises a repeater-type transistor located...

Matches 1 - 20 out of 20