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Match Document Document Title
US20060180580 High speed, laser-based marking method and system for producing machine readable marks on workpieces and semiconductor devices with reduced subsurface damage produced thereby  
An improved method of laser marking semiconductor wafers is provided wherein undesirable subsurface damage to a silicon semiconductor wafer is avoided while providing a relative improvement in...
US20080284048 Alignment mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same  
Provided are an alignment mark with a higher rate of recognition, a semiconductor chip including the alignment mark, a semiconductor package including the semiconductor chip, and methods of...
US20060249859 Metrology system and method for stacked wafer alignment  
Using imaging techniques to determine if stacked wafers are in proper alignment. An infrared radiation source and an infrared camera are positioned on opposing sides of a stacked wafer. The...
US20060027809 Semiconductor device including semiconductor thin film, which is subjected to heat treatment to have alignment mark, crystallizing method for the semiconductor thin film, and crystallizing apparatus for the semiconductor thin film  
Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an...
US20070111477 Semiconductor wafer  
A semiconductor wafer is disclosed for which irradiation of a laser beam forms a modified region due to multiphoton absorption to thereby facilitate dicing of the semiconductor wafer. The...
US20050140030 Scribe street width reduction by deep trench and shallow saw cut  
In a method to singulate a semiconductor wafer (100) into chips, trench streets (107) of predetermined depth (105a) are formed across the first, active wafer surface (102) to define the outline of...
US20120112370 TEMPLATE, METHOD OF FORMING TEMPLATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE  
According to one embodiment, a template includes a pattern part which is provided on a substrate and corresponds to a pattern of a semiconductor device, the pattern of the semiconductor device...
US20070069400 ALIGNMENT MARK, ALIGNMENT APPARATUS AND METHOD, EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD  
An alignment mark including a first mark usable for both coarse alignment measurement in a first direction and fine alignment measurement in the first direction, and a second mark usable for...
US20160005695 PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF  
A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning...
US20100327451 ALIGNMENT MARK  
An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region...
US20090273102 Semiconductor Substrate and Method for Manufacturing the Same  
A semiconductor substrate is provided in which an alignment mark is formed that can be used for an aligment even after the formation of an impurity diffused layer by the planarization of an...
US20050186754 Solid-state imaging apparatus having multiple anti-reflective layers and method for fabricating the multiple anti-reflective layers  
A solid-state imaging apparatus comprising multiple anti-reflective layers which can improve a smear characteristic while suppressing a dark defect and a method for fabricating the multiple...
US20070194466 Overlay measurement mark and pattern formation method for the same  
Fine projection patterns are added to each side of a base mark pattern of an overlay measurement mark. Thus, film separation in the overlay measurement mark can be prevented.
US20060175718 Semiconductor device and method of manufacturing the same  
A semiconductor device includes a semiconductor substrate having a first element isolation trench with a first opening width and a second element isolation trench with a second opening width...
US20070222089 Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device  
Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor...
US20060273385 Trenched MOSFET device with contact trenches filled with tungsten plugs  
A trenched semiconductor power device that includes a trenched gate disposed in an extended continuous trench surrounding a plurality of transistor cells in an active cell area and extending as...
US20100225011 System and Method for Integrated Circuit Fabrication  
A system and method for integrated circuit fabrication is provided. A wafer holding system includes a wafer carrier that holds the wafer at a specified alignment, and a top ring disposed on a top...
US20090102070 Alignment Marks on the Edge of Wafers and Methods for Same  
A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into...
US20080265445 Marks for the Alignment of Wafer-Level Underfilled Silicon Chips and Method to Produce Same  
A semiconductor wafer and the process for aligning wafer level underfill material coated chips with a substrate via alignment marks made visible through laser dicing.
US20050026385 Method for manufacturing a semiconductor device and semiconductor device with overlay mark  
In a method for forming a semiconductor device and a semiconductor device having an overlay mark, a first pattern for the semiconductor device is formed in a semiconductor device formation region...
US20160079182 METHOD FOR PROCESSING A CARRIER AND A CARRIER  
A method for processing a carrier may include forming at least one recess structure at least one of over and in the carrier; and annealing the at least one recess structure such that at least one...
US20150249054 SUBSTRATE ALIGNMENT MARK AND FABRICATING METHOD THEREOF, AND SUBSTRATE  
A substrate alignment mark and a fabricating method thereof, and a substrate are provided. The substrate alignment mark includes a first alignment mark pattern and a second alignment mark pattern...
US20070257288 ALIGNMENT MARK FOR SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE  
An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer,...
US20070210453 Dummy-fill-structure placement for improved device feature location and access for integrated circuit failure analysis  
An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The...
US20120292789 SEMICONDUCTOR WAFER AND METHOD OF PRODUCING THE SAME  
Provided is a method of producing a semiconductor wafer. The method includes forming an alignment mark on a base wafer, forming, on the base wafer in a region that includes the alignment mark, an...
US20080179761 SEMICONDUCTOR PACKAGE HAVING EVAPORATED SYMBOLIZATION  
The package (105) of a semiconductor chip has a surface (105a) of optical reflection and color, and is substantially free of indentations; the material of the package may be selected from a group...
US20060138681 Substrate and lithography process using the same  
Provided are substrates, e.g. semiconductor wafers, whereby the front side of the substrate and the back side of the substrate differ in surface roughness. Also provided are lithography processes...
US20070176305 Alignment mark and overlay inspection mark  
An alignment mark is formed on an underlying layer and disposed on a region in which a semiconductor device is not formed. The alignment mark includes a plurality of strip-shaped patterns...
US20060220265 Alignment mark for semiconductor device, and semiconductor device  
An alignment mark for a semiconductor device is provided. The alignment mark defines a plane pattern and includes a conductive layer embedded in a recessed section provided in an insulation layer,...
US20050244729 Method of measuring the overlay accuracy of a multi-exposure process  
A method of measuring the overlay accuracy of a multi-exposure process is provided. The characteristic of this invention is utilizing a scanning electron microscope for monitoring the overlay...
US20070108638 ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION  
A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line...
US20070069398 Overlay metrology mark  
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular...
US20130009328 ALIGNMENT MARK, SEMICONDUCTOR HAVING THE ALIGNMENT MARK, AND FABRICATING METHOD OF THE ALIGNMENT MARK  
An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the...
US20100052191 Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method  
A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a...
US20080230929 OVERLAY MARK OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE OVERLAY MARK  
Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising...
US20090127722 Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure  
Method for processing at least one spacer structure in a manufacturing process of a semiconductor device, wherein the at least one spacer structure is subjected to at least one etch process step...
US20070099097 Multi-purpose measurement marks for semiconductor devices, and methods, systems and computer program products for using same  
A mark for use in measuring characteristics of a layer of the semiconductor device includes multiple staggered L-shaped patterns including adjacent vertices, and legs that include line segments...
US20070284764 Sensing mechanism for crystal orientation indication mark of semiconductor wafer  
A sensing mechanism for crystal orientation indication mark of semiconductor wafer is provided. The semiconductor wafer includes: a device region formed on a surface of the semiconductor wafer,...
US20050009298 Method for manufacturing semiconductor device  
For marking a package efficiently at low cost, there is provided a dicing sheet 25 having transfer patterns 28A, 28B and an alignment mark 31 disposed at predetermined positions on a main surface...
US20110095410 WAFER LEVEL SEMICONDUCTOR DEVICE CONNECTOR  
This document discusses, among other things, a semiconductor connector including a conductive pad in a recessed pad area on a surface of a dielectric, the dielectric material configured to be...
US20070222088 Overlay Metrology Mark  
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular...
US20050156335 Marks and method for multi-layer alignment  
Marks and a method for multi-layer alignment. A first layer with first alignment marks is formed on a semiconductor substrate, wherein the first alignment marks are separated parallelly by a...
US20160211219 SEMICONDUCTOR DEVICE WITH AT LEAST ONE TRUNCATED CORNER AND/OR SIDE CUT-OUT  
A method of producing a substantially rectangular semiconductor device having at least one corner truncation or corner cut-out or side cut-out, comprises: a) providing a semiconductor substrate;...
US20110074049 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MASK AND SEMICONDUCTOR DEVICE  
A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective...
US20060118974 Structure provided on an overlay region, overlay mark having the structure, and method of forming the overlay mark  
A structure, which may be provided on an overlay region for an overlay mark, may include a first pattern that may project from a peripheral portion of the overlay region that may be defined on a...
US20100001416 WAFER LASER-MARKING METHOD AND DIE FABRICATED USING THE SAME  
A wafer laser-marking method is provided. First, a wafer having a first surface (an active surface) and a second surface (a back surface) opposite to each other is provided. Next, the wafer is...
US20070018341 Contact etching utilizing partially recessed hard mask  
A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is...
US20070200259 Touch panel  
The touch panel of the invention includes an optically transparent upper substrate having an upper conductive layer formed on an undersurface thereof, an optically transparent lower substrate...
US20090312981 ALIGNMENT MARK AND ALIGNMENT METHOD USING THE ALIGNMENT MARK  
An alignment mark structure includes a first pair of first side walls and a second pair of second side walls. The first pair of first side walls faces each other and extends in a first direction....
US20060065985 Substrate edge scribe  
A substrate that is adapted for the fabrication of integrated circuits, having an improved scribe mark. The scribe mark is small enough to fit within an edge exclusion zone of the substrate, is...

Matches 1 - 50 out of 78 1 2 >