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US20150050755 |
METROLOGY MARKS FOR BIDIRECTIONAL GRATING SUPERPOSITION PATTERNING PROCESSES
Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a... |
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US20150048525 |
METROLOGY MARKS FOR UNIDIRECTIONAL GRATING SUPERPOSITION PATTERNING PROCESSES
Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an... |
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US20150228589 |
INDEXING OF ELECTRONIC DEVICES WITH MULTIPLE WEIGHT MARKERS
A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was... |
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US20150076613 |
OVERLAY MARK
An overlay mark comprises a first feature in a first layer. The first feature has a length extending in a first longitudinal direction and a width extending in a second longitudinal direction. The... |
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US20150028500 |
FORMING ALIGNMENT MARK AND RESULTING MARK
Methods for forming an alignment mark and the resulting mark are disclosed. Embodiments may include forming a first shape having rotational symmetry; forming a second shape; and forming an... |
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US20060103034 |
Overlay mark for a non-critical layer of critical dimensions
An overlay mark for monitoring the critical dimension of a non-critical layer, comprising four first bars which are bar-shaped and separated from each other. The four first bars enclose to form a... |
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US20070176305 |
Alignment mark and overlay inspection mark
An alignment mark is formed on an underlying layer and disposed on a region in which a semiconductor device is not formed. The alignment mark includes a plurality of strip-shaped patterns... |
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US20080290530 |
SEMICONDUCTOR DEVICE HAVING PHOTO ALIGNING KEY AND METHOD FOR MANUFACTURING THE SAME
Embodiments consistent with the present invention provide a semiconductor device having a photo aligning key and a method for manufacturing the same. The semiconductor device includes a pattern... |
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US20140264961 |
Invisible Dummy Features and Method for Forming the Same
A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The... |
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US20080230929 |
OVERLAY MARK OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE OVERLAY MARK
Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising... |
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US20110156285 |
INTEGRATED ALIGNMENT AND OVERLAY MARK, AND METHOD FOR DETECTING ERRORS OF EXPOSED POSITIONS THEREOF
An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay... |
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US20140210113 |
ALIGNMENT MARK RECOVERY WITH REDUCED TOPOGRAPHY
When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In... |
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US20110084412 |
INDEXING OF ELECTRONIC DEVICES WITH MULTIPLE WEIGHT MARKERS
A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference... |
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US20060118974 |
Structure provided on an overlay region, overlay mark having the structure, and method of forming the overlay mark
A structure, which may be provided on an overlay region for an overlay mark, may include a first pattern that may project from a peripheral portion of the overlay region that may be defined on a... |
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US20110285036 |
OVERLAY MARK ASSISTANT FEATURE
A method and apparatus for alignment are disclosed. An exemplary apparatus includes a substrate having an alignment region; an alignment feature in the alignment region of the substrate; and a... |
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US20070248898 |
TARGETS FOR ALIGNMENT OF SEMICONDUCTOR MASKS
Alignment of mask layers in semiconductor manufacturing is carried out by using alignment lines having at least one row of diffractively reflecting or scattering features on the lines. The... |
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US20060065985 |
Substrate edge scribe
A substrate that is adapted for the fabrication of integrated circuits, having an improved scribe mark. The scribe mark is small enough to fit within an edge exclusion zone of the substrate, is... |
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US20140002822 |
OVERLAY MARK AND METHOD OF MEASURING THE SAME
A device having an overlay mark over a substrate and a method of adjusting multi-layer overlay alignment using the overlay mark for accuracy are disclosed. The overlay mark includes a first... |
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US20130056886 |
Method and Apparatus of Providing Overlay
Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension... |
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US20110133347 |
METHOD AND APPARATUS OF PROVIDING OVERLAY
Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension... |
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US20070222088 |
Overlay Metrology Mark
An overlay metrology mark for determining the relative position between two or more layers of an integrated circuit structure comprising a first mark portion associated with and in particular... |
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US20100309470 |
ALIGNMENT MARK ARRANGEMENT AND ALIGNMENT MARK STRUCTURE
An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and... |
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US20070099097 |
Multi-purpose measurement marks for semiconductor devices, and methods, systems and computer program products for using same
A mark for use in measuring characteristics of a layer of the semiconductor device includes multiple staggered L-shaped patterns including adjacent vertices, and legs that include line segments... |
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US20130182255 |
OVERLAY MARK AND APPLICATION THEREOF
An overlay mark for checking alignment accuracy between a former layer and a later layer on a wafer is described, including a former pattern as a part of the former layer, and a later pattern as a... |
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US20150002846 |
WAFER ALIGNMENT MARK SCHEME
A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to the... |
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US20130107259 |
OVERLAY TARGET GEOMETRY FOR MEASURING MULTIPLE PITCHES
An overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure... |
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US20100062548 |
PHOTO KEY AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE PHOTO KEY
A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the... |
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US20150187703 |
BOX-IN-BOX OVERLAY MARK
A box-in-box overlay mark is described, including an inner box region and an outer box region surrounding the same, dense narrow trenches in the previous layer in the inner box region and the... |
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US20090085233 |
ALIGNMENT FEATURES FOR PROXIMITY COMMUNICATION
Embodiments of a semiconductor die that includes proximity connectors proximate to a first surface of the semiconductor die are described. This semiconductor die is configured to communicate... |
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US20140362457 |
SLOTTED CONFIGURATION FOR OPTIMIZED PLACEMENT OF MICRO-COMPONENTS USING ADHESIVE BONDING
An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the... |
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US20080203589 |
VARIABLE FILL AND CHEESE FOR MITIGATION OF BEOL TOPOGRAPHY
A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes... |
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US20090312981 |
ALIGNMENT MARK AND ALIGNMENT METHOD USING THE ALIGNMENT MARK
An alignment mark structure includes a first pair of first side walls and a second pair of second side walls. The first pair of first side walls faces each other and extends in a first direction.... |
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US20090001615 |
SEMICONDUCTOR TEST STRUCTURES
Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different... |
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US20100052191 |
Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method
A method of manufacturing an integrated circuit provides a metrology mark (e.g., alignment mark or overlay mark). The method includes forming a first plurality of first structures arranged in a... |
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US20090294995 |
OVERLAY MARK
An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures,... |
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US20120299204 |
OVERLAY MARK AND METHOD FOR FABRICATING THE SAME
A method for fabricating an overlay mark, including the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein... |
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US20070031743 |
Alignment and alignment marks
A lithographic substrate provided with an alignment mark, the alignment mark having a plurality of features spaced apart from one another, each feature being spaced apart from adjacent features by... |
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US20150028499 |
Apparatus and Method for Forming Alignment Features for Back Side Processing of a Wafer
A method for forming an alignment feature for back side wafer processing in a wafer fabrication process involves forming a trench into but not entirely through a wafer from a top side of the... |
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US20050133940 |
Method and structure for protecting an alignment mark
A method and structure for protecting alignment marks. A substrate comprising a plurality of alignment marks is provided, wherein the alignment mark comprises a plurality of trenches. A plurality... |
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US20130009328 |
ALIGNMENT MARK, SEMICONDUCTOR HAVING THE ALIGNMENT MARK, AND FABRICATING METHOD OF THE ALIGNMENT MARK
An alignment mark with a sheet or a layer of copper, which is compatible with a copper process, is provided herein. In one embodiment, a whole sheet of copper (Cu) is used as a background of the... |
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US20140065736 |
DEVICE CORRELATED METROLOGY (DCM) FOR OVL WITH EMBEDDED SEM STRUCTURE OVERLAY TARGETS
Aspects of the present disclosure describe a target for use in measuring a relative position between two substantially coplanar layers of a device. The target includes periodic structures in first... |
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US20090045530 |
MICROELECTRONIC LITHOGRAPHIC ALIGNMENT USING HIGH CONTRAST ALIGNMENT MARK
A microelectronic structure, and in particular a semiconductor structure, includes a substrate that includes an alignment mark comprising a substantially present element that has an atomic number... |
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US20090102069 |
INTEGRATED CIRCUIT SYSTEM WITH ASSIST FEATURE
An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second... |
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US20070108638 |
ALIGNMENT MARK WITH IMPROVED RESISTANCE TO DICING INDUCED CRACKING AND DELAMINATION IN THE SCRIBE REGION
A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line... |
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US20090096116 |
ALIGNMENT MARK AND MEHTOD FOR FORMING THE SAME
The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first... |
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US20130342831 |
DEVICE-LIKE SCATTEROMETRY OVERLAY TARGETS
In one embodiment, a semiconductor target for detecting overlay error between two or more successive layers of a substrate or between two or more separately generated patterns on a single layer of... |
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US20110250710 |
ELECTRICAL ALIGNMENT MARK SET AND METHOD FOR ALIGNING WAFER STACK
An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple... |
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US20090134531 |
OVERLAY MARK AND METHOD FOR FORMING THE SAME
The invention is directed to an overlay mark in a first material layer in an overlay alignment region of a wafer and the first material layer is made from a first material. The overlay mark... |
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US20110169175 |
OVERLAY MARK
An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the... |
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US20090057847 |
Gallium nitride wafer
A gallium nitride wafer 11 has a substantially circular shape. The gallium nitride wafer 11 includes a plurality of stripe regions 13, a plurality of single crystal regions 15, and a visible mark... |