Matches 1 - 50 out of 272 1 2 3 4 5 6 >


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US20130214433 Efficient Non-Integral Multi-Height Standard Cell Placement  
An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion...
US20130154128 Automatic Place and Route Method for Electromigration Tolerant Power Distribution  
The present disclosure relates to an electromigration tolerant power distribution network generated by an automatic place and route (APR) methodology. In some embodiments, an automatic place and...
US20130087932 INTEGRATED CIRCUITS AND METHODS OF DESIGNING THE SAME  
A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard...
US20080111253 INTEGRATED CIRCUIT HAVING A DISTRIBUTED NETWORK OF LANDING PADS  
An electrical device comprising an integrated circuit (IC) having an uppermost layer that includes landing pads that are distributed throughout one side of the IC.
US20070007670 Reworkable bond pad structure  
A bond pad structure includes a plurality of normal bond pads, a conductive structure and a plurality of backup bond pads. The conductive structure has a plurality of blocks, and at least one of...
US20060006533 Motherboard structure for preventing short circuit  
A motherboard for preventing short circuit includes an IC device and a PCB. The IC device has a plurality of tin balls, and the PCB has matching pads with the tin balls of the IC device. The tin...
US20140167293 INTEGRATED CIRCUIT WITH BUMP CONNECTION SCHEME  
An integrated circuit includes first and second bump pads spaced from each other with a first space, configured to receive differential signals for a normal operation, and at least one redundant...
US20090152595 SEMICONDUCTOR DEVICES AND METHOD OF TESTING SAME  
There are provided a semiconductor device having a pattern which allows electric failures to be sensitively detected at high speeds, and a method of testing the same. In one embodiment, the...
US20110024921 CONTACT LAYOUT STRUCTURE  
A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region,...
US20090008803 LAYOUT OF DUMMY PATTERNS  
A layout of dummy patterns on a wafer having a plurality of pads disposed thereon is described. The layout of the dummy patterns includes having a plurality of dummy patterns spaced apart from...
US20090236758 SEMICONDUCTOR MODULE  
A semiconductor module has a plurality of semiconductor devices arranged on a substrate and mutually connected by signal bus wiring lines. Each pair of first semiconductor devices are connected to...
US20070018340 Integrated circuit pad with separate probing and bonding areas  
A semiconductor device includes an integrated circuit and a pad coupled to the integrated circuit. The pad has a probing area and a bonding area, and a material of the pad has multiple heights...
US20130154099 PAD OVER INTERCONNECT PAD STRUCTURE DESIGN  
A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit....
US20100044886 SEMICONDUCTOR DEVICE HAVING PAIRS OF PADS  
An integrated-circuit semiconductor device includes external electrical connection pads on one face and electrical connection vias under said pads. The electrical connection vias are arranged with...
US20110084365 Through Silicon Via (TSV) Wire Bond Architecture  
A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top...
US20120104604 CRACK ARREST VIAS FOR IC DEVICES  
An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of...
US20100327443 JOINING STRUCTURE AND A SUBSTRATE-JOINING METHOD USING THE SAME  
The present invention concerns a joining structure and a substrate-joining method using the same. The joining structure comprises a substrate, and comprises a plurality of joining patterns which...
US20110062601 GENERATING AN INTEGRATED CIRCUIT IDENTIFIER  
The generation of a chip identifier supporting at least one integrated circuit, which includes providing a cutout of at least one conductive path by cutting the chip, the position of the cutting...
US20050285281 Pad-limited integrated circuit  
An integrated circuit having bond pads disposed in a core logic area. According to one embodiment of the invention, an IC includes a core logic area surrounded by first set of bond pads wherein...
US20080303177 BONDING PAD STRUCTURE  
A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the...
US20080111255 Semiconductor integrated circuit and multi-chip module  
In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and...
US20110180942 INTERCONNECTION STRUCTURE  
An interconnection structure includes: first and second differential signal interconnections provided to transmit a differential signal; and first and second voltage interconnections applied with...
US20100013109 FINE PITCH BOND PAD STRUCTURE  
This invention discloses an integrated circuit (IC) chip which comprises a first, second and third bonding pad connected exclusively to a first, second and third probing pad, respectively, wherein...
US20110042832 EXTENDABLE CONNECTOR AND NETWORK  
Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled...
US20070222086 On-die bond wires system and method for enhancing routability of a redistribution layer  
An integrated circuit includes a first die and a second die positioned in a package. The first die has a redistribution layer formed on the die and including a plurality of relocated bond pads....
US20090174084 VIA OFFSETTING TO REDUCE STRESS UNDER THE FIRST LEVEL INTERCONNECT (FLI) IN MICROELECTRONICS PACKAGING  
The invention is directed to an improved microelectronics device that reduces BEOL delamination by reducing the tensile stress imposed on the via which connects first level interconnects with the...
US20110089579 MULTI-CHIP MODULE  
A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is...
US20070152348 ARRAY CIRCUIT SUBSTRATE AND WIRE BONDING PROCESS USING THE SAME  
An array circuit substrate including a plurality of substrate units, a plurality of non-stick test circuits, and a plurality of etching windows is provided. Each of the substrate units has a...
US20110285034 ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES  
Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip...
US20150084212 CLOCK SKEW ADJUSTING METHOD AND STRUCTURE  
A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a...
US20060017176 Bump ball device and placing method thereof  
The present invention provides a bump ball device and a placing method thereof. The bump ball device having a die on which I/O terminal of a plurality of circuit elements are arranged, includes: a...
US20120211902 BOND PAD STRUCTURE  
A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive...
US20050017376 IC chip with improved pillar bumps  
An IC chip with a plurality of improved pillar bumps is disclosed. A chip has a plurality of bonding pads on its active surface. An Under Bump Metallurgy layer (UBM) is formed onto the bonding...
US20060214189 Semiconductor device with two or more bond pad connections for each input/output cell and method of manufacture thereof  
A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a...
US20110156282 Gate Conductor Structure  
A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species...
US20080150168 Information storage medium on which is stored an interconnection program, interconnection method, interconnection apparatus, and semiconductor device  
Conventionally, an excessively strict current limitation is often adopted. An interconnection apparatus includes an acquisition unit and a decision unit. The acquisition unit serves to acquire a...
US20050269718 Optimized driver layout for integrated circuits with staggered bond pads  
One embodiment of a method and system is disclosed. The method configures a plurality of bond pads on a die arranged in a staggered array. The staggered array includes an inner and outer ring of...
US20060091535 Fine pitch bonding pad layout and method of manufacturing same  
Disclosed herein is a bonding pad formed on an IC chip for electrically coupling the IC chip to another device or component, and associated methods of manufacturing the bonding pad. In one...
US20090064078 Method of designing a semiconductor integrated circuit having a dummy area and the semiconductor integrated circuit thereof  
An exemplary semiconductor integrated circuit is formed on a surface of a semiconductor chip includes a circuit region and a dummy region on the surface of the semiconductor chip. The circuit...
US20140246791 14 LPM CONTACT POWER RAIL  
A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active...
US20070108619 Bonding pad with high bonding strength to solder ball and bump  
A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder...
US20080088038 Bond pad structures and integrated circuit chip having the same  
Bonding pad structures and integrated circuits having the same are provided. An exemplary embodiment of a bond pad structure comprises a bond pad layer. A passivation layer partially covers the...
US20080164622 Wiring board  
A difference in delay of signal transmission due to the wiring within a board is minimized. A wiring board includes wiring for connecting terminals included in one of a plurality of semiconductor...
US20120104632 PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT COMPRISING AN ANALOG BLOCK AND A DIGITAL BLOCK, AND CORRESPONDING INTEGRATED CIRCUIT  
The integrated circuit comprises an analog block and a digital block in and/or on the same substrate. At least part of a first integrated-circuit portion (BA2) corresponding to the analog block is...
US20090283921 CONTACT LAYOUT STRUCTURE  
A contact layout structure includes a substrate having at least a first region defined thereon, plural sets of first contact layouts positioned along a predetermined direction in the first region,...
US20110108982 PRINTED CIRCUIT BOARD  
A printed circuit board includes a body part formed with connection pads on a first surface thereof; and a warpage compensating part formed over the first surface of the body part and having a...
US20060022353 Probe pad arrangement for an integrated circuit and method of forming  
An integrated circuit die (10) includes a substrate (64), a plurality of metal interconnect layers (62) formed over the substrate (64), an insulating layer (58), a first pad (12), a second pad...
US20090166894 SEMICONDUCTOR INTEGRATED CIRCUIT  
The present invention reduces the congestion of signal wires around an ESD protection circuit resulting from the presence of a connecting wire above the ESD protection circuit. The connecting wire...
US20100225009 INTEGRATED CIRCUIT ASSEMBLIES WITH ALIGNMENT FEATURES AND DEVICES AND METHODS RELATED THERETO  
A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface...
US20060001180 In-line wire bonding on a package, and method of assembling same  
A wire-bonding substrate includes in-line wire bonds that are substantially of the same pitch on the die bond pads as on the substrate bond pads. A wire-bonding substrate also includes staggered...

Matches 1 - 50 out of 272 1 2 3 4 5 6 >