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US20110227234 |
MULTI-FUNCTION CARD DEVICE
A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection... |
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US20050012225 |
Wafer-level chip scale package and method for fabricating and using the same
A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned... |
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US20160284619 |
Semiconductor Package with Embedded Die
A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a... |
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US20060138660 |
Copper interconnect
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a... |
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US20060071336 |
Copper interconnect
An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device.... |
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US20060055060 |
Copper interconnect
An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device.... |
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US20070228583 |
Methods of bridging lateral nanowires and device using same
A semiconductor nanowire is grown laterally. A method of growing the nanowire forms a vertical surface on a substrate, and activates the vertical surface with a nanoparticle catalyst. A method of... |
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US20090140438 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Wirings each having a side face with a different angle, which is made accurately, in a desired portion over one mother glass substrate are provided without increasing the steps. With the use of a... |
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US20110298121 |
POWER SEMICONDUCTOR DEVICE
A power semiconductor device according to the present invention includes a heat sink made of Cu and having a thickness of 2 to 3 mm, an insulating substrate bonded on the heat sink with... |
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US20060017161 |
Semiconductor package having protective layer for re-routing lines and method of manufacturing the same
An apparatus and method for manufacturing a semiconductor package are disclosed. The apparatus may include at least a semiconductor chip having input/output (I/O) pads arranged on a surface... |
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US20050104222 |
Flip chip device having supportable bar and mounting structure thereof
A flip chip device may have a semiconductor chip with an active surface on which chip pads and a protective layer may be provided. Solder bumps may be provided on the active surface and... |
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US20160086909 |
METHODS AND APPARATUSES FOR SHAPING AND LOOPING BONDING WIRES THAT SERVE AS STRETCHABLE AND BENDABLE INTERCONNECTS
A capillary tool for use in feeding, bending, and attaching a bonding wire between a pair of bond pads includes a body and a heating element. The body has an internal tube that extends from a... |
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US20120061816 |
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Provided are a semiconductor package and method of fabricating the same. The package includes an interconnection substrate, a semiconductor chip mounted on the interconnection substrate, a lateral... |
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US20070187840 |
Nanoscale probes for electrophysiological applications
A device comprising a planar integrated circuit that includes an array of electrodes and at least one nanostructure, having a major axis, in electrical contact with at least one electrode. The... |
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US20160013159 |
CHIP, CHIP-STACKED PACKAGE USING THE SAME, AND METHOD OF MANUFACTURING THE CHIP-STACKED PACKAGE
A chip including a chip body, the chip body including a surface portion and edges surrounding the surface portion, at least one of the edges having a sloped portion, and a side pad on the sloped... |
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US20050263873 |
Interposer substrate, semiconductor package and semiconductor device, and their producing methods
A semiconductor package comprises a semiconductor chip, an interposer substrate, a plurality of unfilled end face through holes arrayed at the periphery of the semiconductor package, a plurality... |
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US20060097402 |
Semiconductor device having flip-chip package and method for fabricating the same
A semiconductor device having a flip-chip package and a method for fabricating the same are provided. A flip-chip package after being tested to be functionally workable is mounted on a carrier and... |
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US20050275089 |
Package and method for packaging an integrated circuit die
An integrated circuit assembly includes a lead frame having a plurality of leads with inner portions. A thermally-conductive clip member is bonded to the inner portions of the leads such that the... |
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US20080093749 |
Partial Solder Mask Defined Pad Design
A solder ball pad that includes a substrate and a bonding pad attached to the substrate. The bonding pad has a bonding pad surface and a bonding pad edge. The solder ball pad also includes a... |
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US20080029763 |
Transmission Circuit, Connecting Sheet, Probe Sheet, Probe Card, Semiconductor Inspection System and Method of Manufacturing Semiconductor Device
A probe sheet or a connecting sheet with good transmission characteristics and flexibility comprising contact terminals capable of contacting at a plurality of points and in high density, without... |
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US20060197211 |
Semiconductor device and method of stacking semiconductor chips
In a semiconductor device, two or more semiconductor chips are stacked, a first semiconductor chip has electrical contact pads at such positions that form a mirror image of electrical contact pads... |
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US20090085222 |
ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF
There are provided a plurality of semiconductor apparatuses judged as good items in electrical and functional inspections while having internal connection terminals disposed on electrode pads of... |
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US20070257343 |
DIE-ON-LEADFRAME (DOL) WITH HIGH VOLTAGE ISOLATION
A high voltage semiconductor module has a leadframe with spaced pads which is connected to a heat sink plate by a curable insulation layer on the top of the plate. Semiconductor die may be... |
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US20060175712 |
High performance IC package and method
A novel wire-based interconnect IC package is described as well as the method of designing and the method of producing the IC package. The IC package includes one or more signal carrying wires as... |
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US20050133897 |
Stack package with improved heat radiation and module having the stack package mounted thereon
A stack package with improved heat radiation capability and a module having the stack package mounted thereon are provided in which the back surfaces of first and second chips are exposed through... |
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US20120286405 |
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to the present invention includes a substrate, a semiconductor element which is mounted on the substrate, a protecting film which covers at least a part of the... |
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US20080048344 |
HIGH PERFORMANCE IC PACKAGE AND METHOD
A novel wire-based interconnect IC package is described as well as the method of designing and the method of producing the IC package. The IC package includes one or more signal carrying wires as... |
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US20050029675 |
Tin/indium lead-free solders for low stress chip attachment
Some embodiments of the present invention include lead-free solders for use in low stress component attachments. |
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US20060208349 |
Semiconductor device and manufacturing method for the same
A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can... |
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US20060108676 |
Multi-chip package using an interposer
A method and apparatus for multi-chip packages that are closely coupled using an interposer is disclosed. A top single chip or multi-chip encapsulated package with bottom side contacts is formed... |
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US20060071349 |
Semiconductor device and semiconductor device unit
A semiconductor device, comprising: a flexible substrate; at least one semiconductor element; at least one electrode for external connection, the element and the electrode being formed on a front... |
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US20060012042 |
Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same
A wire-bonding substrate is described. The wire-bonding substrate includes a copper metallization and a gold surface finish disposed above and on the copper metallization. The gold surface finish... |
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US20070222087 |
SEMICONDUCTOR DEVICE WITH SOLDERABLE LOOP CONTACTS
A method of easily manufacturing reliable solder contacts on semiconductor dies are made in the shape of a loop made from metal wires or ribbons that may be coated with other solderable metals.... |
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US20100244281 |
FLEXIBLE PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME
Objects of the present invention is to provide a flexible printed wiring board which has a simple structure, which can be produced at low cost, and which can effectively dissipate heat generated... |
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US20070246821 |
Utra-thin substrate package technology
A semiconductor package assembly having reduced stresses and a method for forming the same are provided. The method includes providing a package substrate comprising a base material, forming an... |
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US20050224932 |
Electrically conductive wire
A method of soldering comprises disposing first and second balls of solder adjacent one another on a wire; disposing flux on the wire between and in contact with both of the first and second balls... |
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US20050121805 |
Semiconductor device and a method of manufacturing the same
A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the... |
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US20100171200 |
SEMICONDUCTOR CHIP PACKAGE
A semiconductor chip package includes a main board; a ceramic substrate having a cavity within which at least one chip is electrically mounted, the cavity being placed at a lower portion of the... |
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US20050285253 |
Forming buried via hole substrates
A preformed copper plug may be inserted into a via hole in a package substrate. The opposed surfaces of the copper preform may be covered with a solder material. Copper foils may then be applied... |
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US20050258550 |
Circuit board and semiconductor device using the same
There is provided a thinner high frequency power module structure having reduced the mounting area. An insulated board is provided with a composite metal board in which the Cu2O powder particles... |
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US20050151268 |
Wafer-level assembly method for chip-size devices having flipped chips
A method for assembling a whole semiconductor wafer (101) with a plurality of device units (120) having metal contact pads. Each contact pad has a patterned barrier metal layer and a metal stud... |
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US20150076714 |
MICROELECTRONIC ELEMENT WITH BOND ELEMENTS TO ENCAPSULATION SURFACE
A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the... |
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US20100127402 |
Interconnect System without Through-Holes
Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use... |
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US20070290373 |
Multilayer bonding ribbon
A bonding wire takes the form of a ribbon, and a bond includes such a bonding wire. The bonding wire includes at least two layers having different current carrying capacity. |
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US20060244156 |
Bond pad structures and semiconductor devices using the same
Bond pad structures and semiconductor devices using the same. An exemplary semiconductor device comprises a substrate. An intermediate structure is formed over the substrate. A bond pad structure... |
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US20050133928 |
Wire loop grid array package
A device comprising a workpiece (401) with a surface (401a) including a center (402) and an array of bond pads (420), further an array of interconnects (405) of uniform height. Each of these... |
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US20100258955 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a... |
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US20050275096 |
Pre-doped reflow interconnections for copper pads
A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120)... |
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US20050067712 |
Semiconductor apparatus and method of fabricating the same
A semiconductor apparatus includes a first conductive film and a second conductive film provided on respective sides of an insulating resin film. A circuit element is mounted on the second... |
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US20080191343 |
Integrated circuit package having large conductive area and method for fabricating the same
An integrated circuit package having large conductive area and method for fabricating the same is provided. The package includes an integrated circuit chip having upper and lower surfaces and a... |