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US20110215472 Through Silicon via Bridge Interconnect  
An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The...
US20070262463 Semiconductor substrate-based interconnection assembly for semiconductor device bearing external elements  
The present invention relates to a method of forming interconnections for a temporary package, wherein the interconnections are capable of receiving solder balls on a die, partial wafer or wafer...
US20170186727 DISCRETE FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS  
Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A flexible integrated circuit system is...
US20150137368 LANDING STRUCTURE FOR THROUGH-SILICON VIA  
Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of...
US20130069246 METHODS OF FORMING ELECTRONIC DEVICES  
Methods of forming electronic devices are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find...
US20120280403 Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die  
A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating...
US20120280402 Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die  
A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating...
US20100200999 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME  
A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is...
US20150041992 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS  
A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the...
US20120038045 Stacked Semiconductor Device And Method Of Fabricating The Same  
A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second...
US20100193952 Integrated circuit die containing particale-filled through-silicon metal vias with reduced thermal expansion  
A method, apparatus and system with an electrically conductive through hole via of a composite material with a matrix forming a continuous phase and embedded particles, with a different material...
US20060027934 Silicon chip carrier with conductive through-vias and method for fabricating same  
A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or...
US20160329299 FAN-OUT PACKAGE STRUCTURE INCLUDING ANTENNA  
A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first semiconductor package including a first redistribution layer...
US20140103499 ADVANCED HANDLER WAFER BONDING AND DEBONDING  
A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a...
US20120248627 HEAT CONDUCTION FOR CHIP STACKS AND 3-D CIRCUITS  
A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On...
US20100155933 Package for semiconductor devices  
To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will...
US20080251932 Method of forming through-silicon vias with stress buffer collars and resulting devices  
A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding...
US20080067694 Post passivation interconnection schemes on top of IC chip  
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or...
US20080067693 Post passivation interconnection schemes on top of IC chip  
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or...
US20070096331 Semiconductor device and method of manufacturing the same  
A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a...
US20070077761 TECHNIQUE FOR FORMING A COPPER-BASED METALLIZATION LAYER INCLUDING A CONDUCTIVE CAPPING LAYER  
By providing a conductive capping layer for metal-based interconnect lines, an enhanced performance with respect to electromigration may be achieved. Moreover, a corresponding manufacturing...
US20070035025 Damascene processing using dielectric barrier films  
Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid...
US20060261392 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first...
US20170062390 Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant  
A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the...
US20160365335 SEMICONDUCTOR CHIP WITH REDUNDANT THRU-SILICON-VIAS  
A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor...
US20160351472 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME  
An integrated circuit device is provided as follows. A connection terminal is disposed on a first surface of a semiconductor structure. A conductive pad is disposed on a second surface, opposite...
US20160204092 SEMICONDUCTOR DEVICE  
The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face...
US20150130080 SEMICONDUCTOR DEVICE STRUCTURES INCLUDING DAMASCENE STRUCTURES  
A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an...
US20150084196 Devices Formed With Dual Damascene Process  
Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench...
US20140327149 DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME  
An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the...
US20130154106 Stacked Packaging Using Reconstituted Wafers  
An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The...
US20130020719 MICROELECTRONIC DEVICES INCLUDING THROUGH SILICON VIA STRUCTURES HAVING POROUS LAYERS  
A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via...
US20150325553 Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP  
A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die...
US20140077392 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME  
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62...
US20130009320 Semiconductor package and method of manufacturing the same  
There are provided a semiconductor package including an antenna formed integrally therewith, and a method of manufacturing the same. The semiconductor package includes: a semiconductor chip; a...
US20120319293 MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE  
A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway...
US20120086003 SEMICONDUCTOR DEVICE AND TEST SYSTEM FOR THE SEMICONDUCTOR DEVICE  
A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate,...
US20060170110 Through-substrate interconnect structures and assemblies  
Through-substrate interconnect structures and assemblies are disclosed. A substrate includes at least one via passing therethrough. The via may have an enlarged central portion, and one or more...
US20060151887 Interconnection structure having double diffusion barrier layer and method of fabricating the same  
An interconnection structure and a method of fabricating the same are provided. The interconnection structure includes an interlayer insulating layer having a structure comprising a via hole...
US20050200027 Conductive through wafer vias  
Methods for fabricating a conductive contact (through-via) through a full thickness of a substrate such as a semiconductor wafer or interposer substrate, and semiconductor devices and systems...
US20170148713 CONNECTION MEMBER, SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE  
A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric...
US20150162265 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME  
Semiconductor packages including chips having through silicon vias (TSVs) and methods of manufacturing the same may be provided to provide reliable and thinner semiconductor packages by mitigating...
US20140197546 PAD STRUCTURES AND WIRING STRUCTURES IN A VERTICAL TYPE SEMICONDUCTOR DEVICE  
Step shape pad structure and wiring structure in vertical type semiconductor device are include a first conductive line having a first line shape and including first pad regions at an upper...
US20130292846 SEMICONDUCTOR PACKAGE  
Provided is a semiconductor package including a first semiconductor chip and a second semiconductor chip respectively disposed at a bottom and at a top so that active surfaces thereof face each...
US20130082402 SEMICONDUCTOR DEVICE  
A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including...
US20130049225 STACKED INTEGRATED CIRCUIT PACKAGES THAT INCLUDE MONOLITHIC CONDUCTIVE VIAS  
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer...
US20120261834 SEMICONDUCTOR DEVICE  
A semiconductor device with a TSV and a shelter is provided. The semiconductor device includes a substrate, a circuit area, at least a TSV and a shelter. The circuit area and the TSV are disposed...
US20120228751 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME  
A semiconductor package and method of manufacture are provided. The semiconductor package may include a package substrate, a semiconductor chip, a molding member and a grounding member. The...
US20110272822 Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors  
A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the...
US20100252930 Method for Improving Performance of Etch Stop Layer  
A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes...