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US20140175662 POWER LAYOUT FOR INTEGRATED CIRCUITS  
An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply...
US20130256893 BONDING PAD STRUCTURE WITH DENSE VIA ARRAY  
A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is...
US20110140278 OPTICAL PROXIMITY CORRECTION AWARE INTEGRATED CIRCUIT DESIGN OPTIMIZATION  
An EDA method is implemented for modifying a layout file after place and route. The method includes storing a library of shape modifications for cells in the design library used for implementation...
US20140239505 Bump-on-Trace Methods and Structures in Packaging  
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder...
US20110127678 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED CIRCUITRY AND POST  
An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having...
US20110012264 OPTOELECTRONIC DEVICE WITH HEAT SPREADER UNIT  
Optoelectronic devices with heat spreader units are described. An optoelectronic device includes a back-contact optoelectronic cell including a plurality of back-contact metallization regions. One...
US20150235951 LATERAL-DIMENSION-REDUCING METALLIC HARD MASK ETCH  
A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is...
US20130043556 SIZE-FILTERED MULTIMETAL STRUCTURES  
A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A...
US20150014712 SOURCE DRIVER INTEGRATED CIRCUIT AND DISPLAY DEVICE COMPRISING SOURCE DRIVER INTEGRATED CIRCUIT  
A source driver integrated circuit comprises a common node; a plurality of pads for inputting power, a portion of which are connected to an external power source and the remainder of which are...
US20130256898 Optimizing Layout of Irregular Structures in Regular Layout Context  
A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular...
US20150048513 METHOD FOR OBTAINING THREE-DIMENSIONAL ACTIN STRUCTURES AND USES THEREOF  
The present invention relates to a method for preparing three-dimensional actin structures having a well-defined shape and displaying improved mechanical rigidity. This method comprises the steps...
US20110031627 Reducing Crosstalk In The Design Of Module Nets  
A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design...
US20120001340 METHOD AND SYSTEM FOR ALIGNMENT OF INTEGRATED CIRCUITS  
Alignment for electronic devices using a template having holes to align the protrusions of one or more integrated circuits. There are least one integrated circuit having a plurality of protrusions...
US20120193804 OHMIC CONNECTION USING WIDENED CONNECTION ZONES IN A PORTABLE ELECTRONIC OBJECT  
The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing...
US20130328205 INTEGRATED CIRCUITS HAVING A CONTINUOUS ACTIVE AREA AND METHODS FOR FABRICATING SAME  
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a standard cell having a first boundary, a second boundary...
US20150194396 BOND PAD HAVING A TRENCH AND METHOD FOR FORMING  
A conductive structure is formed in a last metal layer of an integrated circuit. Passivation material is patterned over a portion of the conductive structure. A first trench is patterned around a...
US20150221595 Impedance Controlled Electrical Interconnection Employing Meta-Materials  
A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The...
US20120038054 IMPEDANCE CONTROLLED ELECTRICAL INTERCONNECTION EMPLOYING META-MATERIALS  
A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The...
US20120049373 Integrated Circuit Including Interconnect Levels  
An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper...
US20130087925 Packaging Structures of Integrated Circuits  
A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.
US20100320609 WETTING PRETREATMENT FOR ENHANCED DAMASCENE METAL FILLING  
Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed...
US20150187696 Interconnect Structure and Method of Forming the Same  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive...
US20140027918 CROSS-COUPLING BASED DESIGN USING DIFFUSION CONTACT STRUCTURES  
An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a...
US20140183751 THREE-DIMENSIONAL STRUCTURE IN WHICH WIRING IS PROVIDED ON ITS SURFACE  
One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a...
US20100301487 IMPROVEMENTS IN OR RELATING TO INTEGRATED CIRCUIT RELIABILITY  
A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect...
US20140332971 METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT  
An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection...
US20150171029 INVERSE NANOSTRUCTURE DIELECTRIC LAYERS  
Embodiments of the present disclosure describe dielectric layers and methods for their fabrication and use. In some embodiments, a dielectric layer may include a dielectric material and a...
US20090321944 SEMICONDUCTOR DEVICE WITH IMPROVED INTERCONNECTION OF CONDUCTOR PLUG  
The semiconductor device comprises a conductor plug 20 and an interconnection 22 having one end connected directly to an upper part of the conductor plug 20. The conductor plug 20 has a projection...
US20120112352 INTEGRATED CIRCUIT SYSTEM WITH DISTRIBUTED POWER SUPPLY  
An integrated circuit system having an interposer and an integrated circuit with first and second bond pads, the integrated circuit die bonded to the interposer using the first bond pads. The...
US20140097542 FLIP PACKAGING DEVICE  
Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate;...
US20130020712 IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFORMANCE WIRE STRUCTURE  
A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring...
US20130334698 MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONIC ELEMENTS THEREIN  
A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic...
US20110101534 AUTOMATED SHORT LENGTH WIRE SHAPE STRAPPING AND METHODS OF FABRICTING THE SAME  
An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length...
US20120104620 CONTACT PAD ARRAY  
A contact pad array is provided. The contact pad array includes a plurality of first contact pads and a plurality of second contact pads. The first contact pads are arranged along the first...
US20120161856 DIE POWER STRUCTURE  
A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a...
US20140264890 NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE  
One illustrative pillar disclosed herein includes a bond pad conductively coupled to an integrated circuit and a pillar comprising a base that is conductively coupled to the bond pad, wherein the...
US20150145111 Electronic component with electronic chip between redistribution structure and mounting structure  
An electronic component which comprises an electrically conductive mounting structure, an electronic chip on the mounting structure, an electrically conductive redistribution structure on the...
US20150221591 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE  
A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms...
US20140252608 Method and Apparatus for Packaging Pad Structure  
Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top...
US20110037175 INTERCONNECTION BETWEEN SUBLITHOGRAPHIC-PITCHED STRUCTURES AND LITHOGRAPHIC-PITCHED STRUCTURES  
An interconnection between a sublithographic-pitched structure and a lithographic pitched structure is formed. A plurality of conductive lines having a sublithographic pitch may be...
US20090289372 Power Supply Network  
A power supply network (2) for an integrated circuit is provided, the power supply network (2) comprising a supply grid (4); a plurality of supply pads (6), each supply pad (6) being in electrical...
US20140252639 INTEGRATED CIRCUIT DEVICE, METHOD FOR PRODUCING MASK LAYOUT, AND PROGRAM FOR PRODUCING MASK LAYOUT  
According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an...
US20120273957 CHIP-PACKAGING MODULE FOR A CHIP AND A METHOD FOR FORMING A CHIP-PACKAGING MODULE  
A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first...
US20090020877 TRANSMISSION LINE STRUCTURE AND SIGNAL TRANSMISSION STRUCTURE  
A transmission line structure includes a routing trace, a doped region and a first guard trace. The routing trace is disposed over a substrate. The doped region is disposed in the substrate and...
US20140035152 Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same  
A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which...
US20060053399 Semiconductor device, designing device, layout designing method, program and storage medium  
A designing device for designing a layout of a semiconductor device includes a layout position candidate extracting unit for obtaining layout position candidates of a regulator, a tentatively...
US20100078823 CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE  
A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate...
US20120098136 Hybrid MEMS RF Switch and Method of Fabricating Same  
Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming...
US20150249048 STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN METAL TRACE OF INTEGRATED CIRCUIT DEVICE  
An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal...
US20110006434 UNDER LAND ROUTING  
An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided...