Matches 1 - 50 out of 53 1 2 >


Match Document Document Title
US20120146227 INTEGRATED CIRCUIT NANOWIRES  
Implementations of encapsulated nanowires are disclosed.
US20120098136 Hybrid MEMS RF Switch and Method of Fabricating Same  
Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming...
US20090032958 Intermetallic conductors  
Intermetallic conductive materials are used to form interconnects in an integrated circuit. In some cases, the intermetallic conductive material may be an intermetallic alloy of aluminum.
US20070102822 Aluminum base target and process for producing the same  
An object of the present invention is to provide an aluminum-based target having a large area which has internal defects such as blow holes reduced to a minimum and has no warp. The aluminum-based...
US20120223432 MOISTURE BARRIER FOR A WIRE BOND  
An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the...
US20140151889 TECHNIQUES FOR ENHANCING DIELECTRIC BREAKDOWN PERFORMANCE  
Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer...
US20120217641 Preventing the Cracking of Passivation Layers on Ultra-Thick Metals  
A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the...
US20070120264 A SEMICONDUCTOR HAVING A COPPER-BASED METALLIZATION STACK WITH A LAST ALUMINUM METAL LINE LAYER  
By replacing, in an otherwise copper-based metallization stack, copper with aluminum in the very last metal line layer, the respective terminal metal layer of conventional semiconductor devices...
US20120248615 MEMS DEVICE AND MANUFACTURING PROCESS THEREOF  
A manufacturing process of a MEMS device divides a substrate for fabricating a MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its...
US20090079081 ELECTRONIC DEVICE WITH WIRE BONDS ADHERED BETWEEN INTEGRATED CIRCUITS DIES AND PRINTED CIRCUIT BOARDS  
An electronic device that has an integrated circuit die with a plurality of contacts pads, a printed circuit board with a plurality of conductors corresponding to each of the contact pads...
US20130161820 METHOD FOR BONDING TWO SILICON SUBSTRATES, AND A CORRESPONDEING SYSTEM OF TWO SILICON SUBSTRATES  
A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding...
US20070114670 Corrosion-resistant aluminum conductive material and process for producing the same  
This invention relates to a corrosion-resistant aluminum conductive material comprising an aluminum material consisting of aluminum or an aluminum alloy and a conductive film formed on the surface...
US20090008786 Sputtering Target  
The present invention provides a sputtering target comprising aluminum and one or more alloying elements including Ni, Co, Ti, V, Cr, Mn, Mo, Nb, Ta, W, and rare earth metals (REM). The addition...
US20100283088 SUBSTRATE-LEVEL INTERCONNECTION AND MICRO-ELECTRO-MECHANICAL SYSTEM  
A micro-electro mechanical system (MEMS) is disclosed, which comprises a substrate; at least one transistor formed on the substrate and electrically connected with a contact plug; at least one...
US20140327062 ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS  
An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide...
US20100276807 FABRICATION OF METAL FILM STACKS HAVING IMPROVED BOTTOM CRITICAL DIMENSION  
A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a...
US20120098137 ELEMENT MOUNTING SUBSTRATE AND SEMICONDUCTOR MODULE  
Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had...
US20110316117 DIE PACKAGE AND A METHOD FOR MANUFACTURING THE DIE PACKAGE  
A die package and a method for manufacturing the die package are provided. The die package includes a second die arranged above a first die, the first die comprising an interconnect region on a...
US20090184421 SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF  
A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component...
US20080122104 Damascene interconnect structure having air gaps between metal lines and method for fabricating the same  
An exemplary damascene interconnect structure includes a substrate (20), a first dielectric layer (21) on the substrate, a plurality of trenches (27) formed in the first dielectric layer, and a...
US20070284754 Power MOSFET contact metallization  
A structure includes a semiconductor device formed in a substrate; an insulator adjacent to the semiconductor device; an electrical contact electrically coupled to the semiconductor device,...
US20120018890 SEMICONDUCTOR DEVICE  
A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material...
US20130087919 LIGHTWEIGHT AND COMPACT THROUGH-SILICON VIA STACK PACKAGE WITH EXCELLENT ELECTRICAL CONNECTIONS AND METHOD FOR MANUFACTURING THE SAME  
A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an...
US20080048346 METHOD OF FABRICATING CONDUCTIVE LINES AND STRUCTURE OF THE SAME  
A method of forming a conductive line suitable for decreasing a sheet resistance of the conductive lines. The method comprises steps of providing a material layer having a conductive layer formed...
US20100171222 HIGH RELIABILITY Au ALLOY BONDING WIRE AND SEMICONDUCTOR DEVICE OF SAME  
[Issues to be Solved] Providing enhanced bonding reliability of Au alloy bonding wire with low electrical resistivity to Al electrode of semiconductor device, and its application of semiconductor...
US20120319283 SEMICONDUCTOR DEVICE HAVING EXTERNAL ELECTRODES EXPOSED FROM ENCAPSULATION MATERIAL  
A semiconductor device includes a semiconductor element including an anode electrode and a cathode electrode, an encapsulating material which covers the semiconductor element, a first external...
US20090194880 WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE  
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of...
US20150054163 Systems and Methods to Enhance Passivation Integrity  
A semiconductor device having enhanced passivation integrity is disclosed. The device includes a substrate, a first layer, and a metal layer. The first layer is formed over the substrate. The...
US20100181676 SUBSTRATE BONDING WITH METAL GERMANIUM SILICON MATERIAL  
A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one...
US20070045855 Method for forming a double embossing structure  
A method for fabricating a circuitry component comprises depositing a first metal layer over a substrate; forming a first pattern-defining layer over said first metal layer, a first opening in...
US20140353833 Stress Compensation Layer to Improve Device Uniformity  
The present disclosure relates to an integrated chip having one or more back-end-of-the-line (BEOL) stress compensation layers that reduce stress on one or more underlying semiconductor devices,...
US20110169168 THROUGH-SILICON VIA FORMED WITH A POST PASSIVATION INTERCONNECT STRUCTURE  
An integrated circuit structure includes a semiconductor substrate, a through-silicon via (TSV) extending into the semiconductor substrate, a pad formed over the semiconductor substrate and spaced...
US20100084682 OHMIC ELECTRODE AND METHOD THEREOF, SEMICONDUCTOR LIGHT EMITTING ELEMENT HAVING THIS  
There are provided an ohmic electrode, which includes a contact layer made of an Al alloy and formed on a nitride-based semiconductor layer functioning as a light emitting layer, a reflective...
US20100065969 Integrated circuit device  
An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of...
US20100032013 SEMICONDUCTOR COMPONENT  
A semiconductor component, in particular in the form of a solar cell, comprises a two-dimensional semiconductor substrate with a first side, a second side which is arranged opposite thereto, a...
US20090267232 METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT  
An integrated circuit (100) is provided that comprises a substrate (140) of silicon and an interconnect (130) in a through-hole extending from the first to the second side of the substrate. The...
US20170077058 SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS  
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the...
US20160240505 METAL JOINING STRUCTURE USING METAL NANOPARTICLES AND METAL JOINING METHOD AND METAL JOINING MATERIAL  
The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined...
US20160111382 VERTICAL BREAKDOWN PROTECTION LAYER  
The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at...
US20160082552 ZN BASED LEAD-FREE SOLDER AND SEMICONDUCTOR POWER MODULE  
Zn based lead-free solder is obtained in which its range of practical melting points is between 300° C. and 350° C. The Zn based lead-free solder includes a Cr content of 0.05 through 0.2 wt %, an...
US20160064350 CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT  
A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a...
US20160013149 ELECTRONIC DEVICE  
An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The main component of...
US20150171016 AL ALLOY FILM FOR SEMICONDUCTOR DEVICE  
Provided is an Al alloy film for semiconductor devices, which has excellent heat resistance and is suppressed in the generation of hillocks even in cases where the Al alloy film is exposed to high...
US20140145341 SEMICONDUCTOR DEVICE  
A semiconductor device includes: a semiconductor element that includes an electrode layer on a surface of the semiconductor element; a low-strength layer that is provided on a surface of the...
US20130214418 Semiconductor Device Package with Slanting Structures  
A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through...
US20130127026 CONNECTING MATERIAL, METHOD FOR MANUFACTURING CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE  
In a connecting material of the present invention, a Zn series alloy layer is formed on an outermost surface of an Al series alloy layer. In particular, in the connecting material, an Al content...
US20130092948 SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE  
The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the...
US20130082387 POWER SEMICONDUCTOR ARRANGEMENT AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR ARRANGEMENT  
In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached...
US20120139118 SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP FOR REDUCING OPEN FAILURES  
A semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface, a chip pad disposed on the first surface of the substrate, and a...
US20120119216 Semiconductor Device, Method of Manufacturing A Semiconductor Device, and Display Device  
A semiconductor device comprises a gate electrode that is provided on a substrate and contains Al or an Al alloy; a gate insulating film that is so formed as to cover at least the upper surface of...

Matches 1 - 50 out of 53 1 2 >