Matches 1 - 50 out of 160 1 2 3 4 >


Match Document Document Title
US20120146227 INTEGRATED CIRCUIT NANOWIRES  
Implementations of encapsulated nanowires are disclosed.
US20150262930 REDUCED HEIGHT M1 METAL LINES FOR LOCAL ON-CHIP ROUTING  
Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of...
US20150091174 METHODS OF FORMING PARALLEL WIRES OF DIFFERENT METAL MATERIALS THROUGH DOUBLE PATTERNING AND FILL TECHNIQUES  
An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface,...
US20130026637 METAL GATE ELECTRODE OF A FIELD EFFECT TRANSISTOR  
An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate...
US20120038051 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME  
A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped...
US20150206872 METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE  
A method of forming a contact structure of a gate structure is provided. In the method, an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate...
US20150221591 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE  
A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms...
US20140061930 OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE  
A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms...
US20150123280 SILICON BURIED DIGIT LINE ACCESS DEVICE AND METHOD OF FORMING THE SAME  
An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the...
US20110298136 MEMS INTEGRATED CHIP WITH CROSS-AREA INTERCONNECTION  
The present invention discloses a MEMS (Micro-Electro-Mechanical System) integrated chip with cross-area interconnection, comprising: a substrate; a MEMS device area on the substrate; a...
US20120098136 Hybrid MEMS RF Switch and Method of Fabricating Same  
Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming...
US20110199569 WIRING BOARD AND LIQUID CRYSTAL DISPLAY DEVICE  
A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires...
US20130040422 Thick Film Pastes For Fire Through Applications In Solar Cells  
Formulations and methods of making solar cell contacts and cells therewith are disclosed. The invention provides a photovoltaic cell comprising a front contact, a back contact, and a rear contact....
US20110079910 DUAL METAL INTERCONNECTS FOR IMPROVED GAP-FILL, RELIABILITY, AND REDUCED CAPACITANCE  
Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.
US20110248403 Dual-Side Interconnected CMOS For Stacked Integrated Circuits  
A stacked integrated circuit (IC) may be manufactured with a second tier wafer bonded to a double-sided first tier wafer. The double-sided first tier wafer includes back-end-of-line (BEOL) layers...
US20120119760 PERFORATED CONTACT ELECTRODE ON VERTICAL NANOWIRE ARRAY  
Disclosed herein is a structure having: a support, a plurality of nanowires perpendicular to the support, and an electrode in contact with a first end of each nanowire. Each nanowire has a second...
US20130187278 STRUCTURE FOR INTERCONNECTING COPPER WITH LOW DIELECTRIC CONSTANT MEDIUM AND THE INTEGRATION METHOD THEREOF  
The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration...
US20080258176 Antimonide-based compound semiconductor with titanium tungsten stack  
An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer....
US20140264887 ORIENTED CRYSTAL NANOWIRE INTERCONNECTS  
Interconnects for semiconductors formed of materials that exhibit crystallographic anisotropy of the resistivity size effect such that line resistivity in one crystallographic orientation becomes...
US20120181698 FORMING THROUGH-SILICON-VIAS FOR MULTI-WAFER INTEGRATED CIRCUITS  
The present invention provides a method for forming a three-dimensional wafer stack having a single metallized stack via with a variable cross-sectional shape. The method uses at least first and...
US20100032842 MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS  
A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen...
US20120248615 MEMS DEVICE AND MANUFACTURING PROCESS THEREOF  
A manufacturing process of a MEMS device divides a substrate for fabricating a MEMS component into two electrically isolated regions, so that the MEMS component and the circuit disposed on its...
US20060211176 Manufacturing method for physical quantity sensor using lead frame and bonding device therefor  
A physical quantity sensor is produced using a lead frame having at least one stage for mounting a physical quantity sensor chip and a frame having leads, wherein the physical quantity sensor chip...
US20090321943 SEED LAYER FOR REDUCED RESISTANCE TUNGSTEN FILM  
Briefly, a memory device comprising a beta phase tungsten seed layer is disclosed.
US20100038749 Contact and VIA Interconnects Using Metal Around Dielectric Pillars  
An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect...
US20130207258 POST-PASSIVATION INTERCONNECT STRUCTURE AMD METHOD OF FORMING SAME  
A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with...
US20130231240 METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS  
A method and apparatus are presented for reducing halide-based contamination within deposited titanium-based thin films. Halide adsorbing materials are utilized within the deposition chamber to...
US20100140804 Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance  
Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.
US20150115444 WAFER ARRANGEMENT, A METHOD FOR TESTING A WAFER, AND A METHOD FOR PROCESSING A WAFER  
According to various embodiments, a wafer arrangement may be provided, the wafer arrangement may include: a wafer including at least one electronic component having at least one electronic contact...
US20060175664 Semiconductor constructions, and methods of forming metal silicides  
The invention includes methods of forming metal silicide. A layer consisting essentially of one or more metal nitrides is formed directly against a silicon-containing region. A layer comprising...
US20150115453 BONDING METHOD USING POROSIFIED SURFACES FOR MAKING STACKED STRUCTURES  
A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The...
US20110147924 WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME  
A wiring substrate includes an insulating layer, a wiring layer buried in the insulating layer, and a connection pad connected to the wiring layer via a via conductor provided in the insulating...
US20080157384 Alignment Key of Semiconductor Device and Method of Manufacturing the Same  
Disclosed is a method of manufacturing an alignment key of a semiconductor device. According to an embodiment, the method includes forming an insulating layer on a semiconductor substrate on which...
US20140131877 STRESS RELIEF STRUCTURES IN PACKAGE ASSEMBLIES  
A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners...
US20130099382 METHOD FOR PRODUCING AN ELECTRICAL FEEDTHROUGH IN A SUBSTRATE, AND A SUBSTRATE HAVING AN ELECTRICAL FEEDTHROUGH  
A method for producing an electrical feedthrough in a substrate includes: forming a first printed conductor on a first side of a substrate which electrically connects a first contact area of the...
US20140327062 ELECTRONIC DEVICES INCLUDING OXIDE DIELECTRIC AND INTERFACE LAYERS  
An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide...
US20120001337 Alignment Mark and Method of Formation  
In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the...
US20090065938 Semiconductor Element and Method for Manufacturing Same  
The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with...
US20100025854 POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES  
Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of the methods include forming an...
US20130049062 Light-Emitting Device  
To provide a highly reliable light-emitting device with less occurrence of cracks in a sealant bonding two facing substrates together. In a light-emitting device, a first substrate including a...
US20130207272 AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING  
An interconnect structure is provided that includes at least one patterned and cured low-k dielectric material located on a surface of a patterned inorganic antireflective coating that is located...
US20090045517 METHOD FOR FORMING TUNGSTEN FILM, FILM-FORMING APPARATUS, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE  
A tungsten film with a lower specific resistance and a lower fluorine concentration over its boundary with the base barrier layer, which adheres to the barrier layer with a high level of...
US20150221613 LARGE CHANNEL INTERCONNECTS WITH THROUGH SILICON VIAS (TSVS) AND METHOD FOR CONSTRUCTING THE SAME  
An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set...
US20120267786 MICROELECTRONIC DEVICES WITH THROUGH-SILICON VIAS AND ASSOCIATED METHODS OF MANUFACTURING  
Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten through-silicon vias comprising forming an...
US20140264886 Forming Fence Conductors Using Spacer Pattern Transfer  
A spacer transfer process produces sub-lithographic patterns of conductive lines in a semiconductor die. A dielectric then a conductive material are deposited onto a face of a semiconductor...
US20140159242 PATTERNING TRANSITION METALS IN INTEGRATED CIRCUITS  
An integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the semiconductor devices, wherein the conductive lines include a transition...
US20140091470 DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY  
Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over...
US20150108651 SELF ALIGNED CONTACT FORMATION  
The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality...
US20120228775 AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING  
The present invention provides a method of fabricating an airgap-containing interconnect structure in which a patternable low-k material replaces the need for utilizing a separate photoresist and...
US20090184421 SEMICONDUCTOR DEVICE WITH HIGH RELIABILITY AND MANUFACTURING METHOD THEREOF  
A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component...

Matches 1 - 50 out of 160 1 2 3 4 >