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US20140175656 USE OF GRAPHENE TO LIMIT COPPER SURFACE OXIDATION, DIFFUSION AND ELECTROMIGRATION IN INTERCONNECT STRUCTURES  
A contiguous layer of graphene is formed on exposed sidewall surfaces and a topmost surface of a copper-containing structure that is present on a surface of a substrate. The presence of the...
US20140252629 Self-Aligned Pitch Split for Unidirectional Metal Wiring  
Self-aligned pitch split techniques for metal wiring involving a hybrid (subtractive patterning/damascene) metallization approach are provided. In one aspect, a method for forming a metal wiring...
US20130288475 METHOD FOR OBTAINING A PALLADIUM SURFACE FINISH FOR COPPER WIRE BONDING ON PRINTED CIRCUIT BOARDS AND IC-SUBSTRATES  
The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding...
US20150084198 INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES  
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a...
US20120299187 Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products  
Embodiments of an aluminum pad thinning in bond pad for fine pitch ultra-thick aluminum pad structures are provided herein. Embodiments include a conductive structure formed on a substrate. A...
US20150084199 Copper Ball Bond Features and Structure  
An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated...
US20140054781 Copper Ball Bond Features and Structure  
An integrated circuit wire bond connection is provided having an aluminum bond pad (51) that is directly bonded to a copper ball (52) to form an aluminum splash structure (53) and associated...
US20120049373 Integrated Circuit Including Interconnect Levels  
An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper...
US20140246772 Passivation Scheme  
An integrated circuit includes a conductive pad disposed over a substrate. A first passivation layer is disposed over the conductive pad. A second passivation layer is disposed over the first...
US20140035148 Bump on Pad (BOP) Bonding structure  
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the...
US20100052174 COPPER PAD FOR COPPER WIRE BONDING  
An integrated circuit package comprising an integrated circuit that includes transistors coupled to copper interconnect structures. The integrated circuit package also comprises copper pads...
US20140097542 FLIP PACKAGING DEVICE  
Disclosed is a flip chip packaging device and structure of interconnections between a chip and a substrate. In one embodiment, a flip chip packaging device can include: (i) a chip and a substrate;...
US20140319689 Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers  
A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad...
US20140048941 Contact Pads with Sidewall Spacers and Method of Making Contact Pads with Sidewall Spacers  
A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad...
US20140175655 CHIP BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF  
A chip bonding structure at least includes a first substrate, a second substrate opposite to the first substrate, and a copper bonding structure sandwiched in between the first and the second...
US20140110847 BUMP-ON-TRACE INTERCONNECTION STRUCTURE FOR FLIP-CHIP PACKAGES  
A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding...
US20050275096 Pre-doped reflow interconnections for copper pads  
A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120)...
US20140145340 Flip Chip Interconnection Structure  
A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip,...
US20130026635 Hybrid Copper Interconnect Structure and Method of Fabricating Same  
A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a...
US20150115442 Redistribution layer and method of forming a redistribution layer  
A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at...
US20110291259 Reliable metal bumps on top of I/O pads after removal of test probe marks  
In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of...
US20140061889 INTERFACIAL ALLOY LAYER FOR IMPROVING ELECTROMIGRATION (EM) RESISTANCE IN SOLDER JOINTS  
Problem To improve the electromigration (EM) resistance of a solder joint.SolutionThe present invention provides a unique structure for an interfacial alloy layer which is able to improve the...
US20080169566 Press-Fit Diode Having a Silver-Plated Wire Termination  
A press-fit diode, e.g., for rectifier applications, includes a diode chip, a base contact for pressing into a substrate, which base contact forms a first terminal of the press-fit diode, and a...
US20060289999 Selective copper alloy interconnections in semiconductor devices and methods of forming the same  
A selective copper alloy interconnection in a semiconductor device is provided. The interconnection includes a substrate, a dielectric formed on the substrate, and a first interconnection formed...
US20130154099 PAD OVER INTERCONNECT PAD STRUCTURE DESIGN  
A design rule checker that performs a maximum pattern density check in a first intermediary metallization layer that underlies a top metallization layer and a pad opening in an integrated circuit....
US20130187277 CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER  
A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings.
US20080061440 COPPER ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE  
The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the...
US20130320545 HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME  
A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a...
US20130147047 Integrated Circuit and Method of Forming an Integrated Circuit  
An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 μm and a ratio of average grain size to thickness of...
US20070120263 Conductor track arrangement and associated production method  
A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks...
US20110254151 METHOD FOR FABRICATING BUMP STRUCTURE WITHOUT UBM UNDERCUT  
A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer....
US20100244266 METALLIC BONDING STRUCTURE FOR COPPER AND SOLDER  
The present invention discloses a metallic bonding structure for copper and solder, which applies to connect at least one electronic element. The metallic bonding structure comprises at least one...
US20150108645 INTEGRATED CRACKSTOP  
A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect...
US20150108650 EUTECTIC SOLDER STRUCTURE FOR CHIP  
The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a...
US20120139017 WIRELESS CHIP  
The invention provides a wireless chip which can secure the safety of consumers while being small in size, favorable in communication property, and inexpensive, and the invention also provides an...
US20140015140 POWER MODULE SUBSTRATE, POWER MODULE, AND METHOD FOR MANUFACTURING POWER MODULE SUBSTRATE  
A power module substrate includes: a ceramics substrate having a surface; and a metal plate connected to the surface of the ceramics substrate, composed of aluminum, and including Cu at a joint...
US20050127516 Small viatops for thick copper connectors  
The present invention relates to integrated circuits comprising a protective overcoat and thick copper connectors. According to one aspect of the inventions, vias in the protective overcoat are...
US20060027931 Semiconductor device and method fabricating the same  
A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the...
US20050140012 Method for forming copper wiring of semiconductor device  
The method for forming the copper wiring of the semiconductor device includes the steps of forming a first copper wiring on a semiconductor substrate having a predetermined low structure,...
US20120211856 PHOTOVOLTAIC CELL CONDUCTOR CONSISTING OF TWO, HIGH-TEMPERATURE AND LOW-TEMPERATURE, SCREEN-PRINTED PARTS  
Method for formation of at least one electrical conductor on a semiconductor material (1), characterized in that it comprises the following steps: (E1)—deposition by serigraphy of a first...
US20060163731 Dual damascene interconnections employing a copper alloy at the copper/barrier interface  
A method of fabricating a dual damascene interconnection is provided. The method begins by forming on a substrate a dielectric layer and forming a via in the dielectric layer. The dielectric layer...
US20080079165 Barrier formation and structure to use in semiconductor devices  
Embodiments of barriers to use in semiconductor devices are presented herein.
US20130026634 Hybrid Interconnect Technology  
In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.
US20140117534 Interconnection Structure  
A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first...
US20140151888 Air-Gap Formation in Interconnect Structures  
A structure includes a substrate, and a first metal line and a second metal line over the substrate, with a space therebetween. A first air gap is on a sidewall of the first metal line and in the...
US20090218696 SEMICONDUCTOR DEVICE INCLUDING A PADDING UNIT  
A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed...
US20150235959 WIRING STRUCTURE AND ELECTRONIC DEVICE EMPLOYING THE SAME  
Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a...
US20150228605 Interconnect Structure and Method of Forming the Same  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the...
US20120080796 DEVICE  
According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a...
US20150235991 BOTTOM PACKAGE WITH METAL POST INTERCONNECTIONS  
A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal...