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Match Document Document Title
US20080042290 Structures Electrically Connecting Aluminum and Copper Interconnections and Methods of Forming the Same  
A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the...
US20080054413 SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME  
A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top...
US20060027931 Semiconductor device and method fabricating the same  
A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the...
US20050140012 Method for forming copper wiring of semiconductor device  
The method for forming the copper wiring of the semiconductor device includes the steps of forming a first copper wiring on a semiconductor substrate having a predetermined low structure,...
US20060035457 Interconnection capacitance reduction  
An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the...
US20060001168 Technique for forming a dielectric interlayer above a structure including closely spaced lines  
By depositing the lower portion of a silicon dioxide interlayer dielectric by means of SACVD or HDP-CVD techniques, the generation of voids may be reliably avoided even for devices having spaces...
US20060125102 Back end of line integration scheme  
A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal...
US20070013009 Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture  
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The...
US20150035157 SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE  
After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern...
US20050173803 Interlayer adhesion promoter for low k materials  
The invention relates to the production of multilayered dielectric structures and to semiconductor devices and integrated circuits comprising these structures. The structures of the invention are...
US20090008783 SEMICONDUCTOR DEVICE WITH PADS OF ENHANCED MOISTURE BLOCKING ABILITY  
A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed...
US20050275106 Electronic isolation device  
A two-terminal electronic isolation device has an anode, a cathode, an integral tunnel junction, and a current-injection layer. The current-injection layer comprises a silicon-rich oxide.
US20150130065 method to etch cu/Ta/TaN selectively using dilute aqueous Hf/h2so4 solution  
Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the...
US20100276805 INTEGRATED CIRCUIT CHIP WITH REDUCED IR DROP  
An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion...
US20110304048 SEMICONDUCTOR APPARATUS  
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a...
US20060099826 Method of forming an insulation film and semiconductor device having the insulation film  
In a method which forms an insulation film using ALD (Atomic Layer Deposition) and which includes a first step of forming deposited silicon atoms on an objective surface by depositing silicon...
US20080054470 Semiconductor Device and Method of Fabricating the Same  
The present invention provides a semiconductor device which is capable of enhancing adhesion at an interface between a wire-protection film and copper, suppressing dispersion of copper at the...
US20060118955 Robust copper interconnection structure and fabrication method thereof  
An interconnect structure has a silicon nitride layer overlying a substrate with a conductive region, a silicon carbide layer overlying the silicon nitride layer, and a dielectric layer having a...
US20070007656 Semiconductor device and methods thereof  
An insulation interlayer having first contact holes exposing first contact pads is formed on a semiconductor structure having the first and second contact pads. Conductive patterns connected to...
US20050242435 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging  
The introduction of dielectric material of enhanced mechanical stability, such as silicon dioxide or fluorine-doped silicon dioxide, into the via level of a low-k interconnect structure provides...
US20090294969 SEMICONDUCTOR CONTACT FORMATION SYSTEM AND METHOD  
The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This...
US20070096325 Semiconductor apparatus  
In the present invention, a wiring layer comprises wirings respectively having different sheet resistance values, or a contact for connecting opposing wiring layers comprises contacts having...
US20060180934 Wiring structures for semiconductor devices  
Wiring structures of semiconductor devices and fabrication methods thereof. A metal layer electrically connected to at least one vertical connection formed in an insulating layer is provided. A...
US20140035146 METAL WIRING OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME  
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying...
US20090008782 INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF  
An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is...
US20050263901 SEMICONDUCTOR DEVICE FORMED BY IN-SITU MODIFICATION OF DIELECTRIC LAYER AND RELATED METHODS  
Disclosed is a semiconductor device with a continuously-deposited dielectric layer having different etch resistances through its depth and methods of manufacturing such a device. Specifically,...
US20090160059 Semiconductor Device Having Improved Adhesion and Reduced Blistering Between Etch Stop Layer and Dielectric Layer  
One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first...
US20090057907 INTERCONNECTION STRUCTURE  
An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and...
US20060138667 Method for forming an intermetal dielectric layer in a semiconductor device using HDP-CVD, and a semiconductor device manufactured thereby  
A method for forming an intermetal dielectric layer in a semiconductor device using high density plasma chemical vapor deposition (HDP-CVD), and a semiconductor device manufactured thereby. The...
US20120280396 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE  
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62...
US20120273953 SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE  
The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62...
US20080029853 INTEGRATED CIRCUIT SYSTEM WITH CONTACT FILM  
A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the...
US20070205516 Low-k dielectric layer, semiconductor device, and method for fabricating the same  
Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The...
US20070069387 Semiconductor device and method of forming the same  
Provided is a method of forming a contact hole. The method includes: depositing an interlayer insulating layer on a semiconductor substrate on which a dummy region and an active region are...
US20060226549 Semiconductor device and fabricating method thereof  
A semiconductor device and a fabrication method thereof. The semiconductor device has a substrate with a first conductive area, a dielectric layer formed of a low dielectric constant material...
US20050156199 Method of forming a CMOS device  
In a method of forming a CMOS device, first and second conductive structures are formed on a substrate. An insulation layer is formed on the substrate having the first and second conductive...
US20170154815 HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS  
In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting...
US20170084487 SEAM HEALING OF METAL INTERCONNECTS  
Embodiments of the present disclosure describe removing seams and voids in metal interconnects and associated techniques and configurations. In one embodiment, a method includes conformally...
US20170011998 SEMICONDUCTOR INTERCONNECT STRUCTURES  
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to...
US20170005100 SEMICONDUCTOR DEVICE INCLUDING DUMMY METAL  
A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically...
US20160379932 INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER  
An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor...
US20160336216 AIR-GAP SCHEME FOR BEOL PROCESS  
The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level...
US20160329236 Semiconductor Structures and Methods of Manufacturing the Same  
A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in...
US20160268200 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF  
A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer,...
US20160240483 INTERCONNECT STRUCTURES AND METHODS OF FORMATION  
Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a...
US20160225711 SEMICONDUCTOR DEVICE  
A semiconductor device includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the...
US20160197011 Subtractive Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects  
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer...
US20160172298 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME  
A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact...
US20150311158 METHOD OF FORMING A HIGH DENSITY DIELECTRIC ETCH-STOP LAYER  
Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged...
US20150294933 PATTERN BETWEEN PATTERN FOR LOW PROFILE SUBSTRATE  
An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned...

Matches 1 - 50 out of 57 1 2 >