Matches 1 - 50 out of 437 1 2 3 4 5 6 7 8 9 >


Match Document Document Title
US20130256893 BONDING PAD STRUCTURE WITH DENSE VIA ARRAY  
A bonding pad structure includes a substrate and a first conductive island formed in a first dielectric layer and disposed over the substrate. A first via array having a plurality of vias is...
US20140061925 LOW RESISTIVITY GATE CONDUCTOR  
Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown...
US20150235946 REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS  
A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have...
US20050006770 Copper-low-K dual damascene interconnect with improved reliability  
A dual damascene-based interconnect structure which includes a liner of aluminum-0.5% copper alloy. The alloy can be implemented by depositing the alloy using a conventional PVD technique. To...
US20060220250 Crack stop and moisture barrier  
A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line....
US20080237869 STRUCTURE AND METHOD FOR LOW RESISTANCE INTERCONNECTIONS  
A method of forming an interconnection in a semiconductor device includes forming a first liner in a dielectric layer therein; depositing a tungsten filler on top of the first liner; performing...
US20130320544 CORROSION/ETCHING PROTECTION IN INTEGRATION CIRCUIT FABRICATIONS  
A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene...
US20130200521 INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL  
Back-end-of-line (BEOL) wiring structures and inductors, methods for fabricating BEOL wiring structures and inductors, and design structures for a BEOL wiring structure or an inductor. A feature,...
US20070114667 Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing  
Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad...
US20070013075 MODULAR CONTAINMENT STRUCTURE  
A modular containment system which has a plurality of stackable building elements, including two or more peripheral sidewall members, a roof and a base. Means are provided for coupling each of the...
US20050206000 Barrier for copper integrated circuits  
An integrated circuit copper interconnect structure is formed by forming a dielectric layer (90) over a semiconductor substrate (10). Trenches (110) and vias (120) are formed in the dielectric...
US20140332963 INTERCONNECT WITH HYBRID METALLIZATION  
An electronic interconnect structure having a hybridized metal structure near regions of high operating temperature on an integrated circuit, and methods of making the same. The hybridized metal...
US20080296771 METHODS OF FABRICATING SILICON CARBIDE POWER DEVICES BY AT LEAST PARTIALLY REMOVING AN N-TYPE SILICON CARBIDE SUBSTRATE, AND SILICON CARBIDE POWER DEVICES SO FABRICATED  
A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the...
US20150214165 BONDING PAD STRUCTURE WITH DENSE VIA ARRAY  
A bonding pad structure comprises a first dielectric layer, a first conductive island in a second dielectric layer over the first dielectric layer and a via array having a plurality of vias in a...
US20050035457 Interconnecting structure with dummy vias  
First wirings and first dummy wirings are in a p-SiOC film on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected...
US20060017153 Interconnections of semiconductor device and method of forming the same  
An interconnection structure includes a substrate containing a first lower interconnection and a pair of second interconnections separated from each other by a predetermined distance, and a...
US20080099877 DAMAGE PROPAGATION BARRIER AND METHOD OF FORMING  
A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse...
US20060001163 Groundless flex circuit cable interconnect  
Embodiments of the present invention include an apparatus, method, and/or system for using a groundless flex circuit cable to interconnect semiconductor packages.
US20060170105 Semiconductor device featuring probe area definition mark for defining probe area in electrode pad, and proof test system for proving proper contact of test probe with probe area  
In a semiconductor device including a semiconductor substrate, a multi-layered wiring structure is formed on the semiconductor substrate, and an electrode pad is formed on the multi-layered wiring...
US20150145135 Electrically Conductive Laminate Structures  
Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the...
US20140264881 METHODS AND STRUCTURES TO FACILITATE THROUGH-SILICON VIAS  
In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality...
US20070262454 Semiconductor device and wiring auxiliary pattern generating method  
An area with a low via pattern density is extracted from a semiconductor integrated circuit that includes the first wirings and the second wirings disposed on the upper layer of the first wirings,...
US20050062162 Pad structure of semiconductor device for reducing or inhibiting wire bonding cracks  
A pad structure of semiconductor device have a special via pattern to divide the IMD layer into separated IMD blocks, so that the wire bonding cracks are reduced or completely inhibited. According...
US20060027931 Semiconductor device and method fabricating the same  
A semiconductor device includes: a semiconductor substrate; an insulating film provided on the semiconductor substrate; a plurality of copper interconnections provided on the same level in the...
US20070164436 DUAL METAL INTERCONNECTION  
Embodiments relate to a dual metal interconnection structure of a semiconductor device and a method for manufacturing the same. In embodiments, the dual metal interconnection structure may include...
US20070284748 Copper interconnects with improved electromigration lifetime  
The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and...
US20090121357 DESIGN STRUCTURE FOR BRIDGE OF A SEMINCONDUCTOR INTERNAL NODE  
A design structure for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The...
US20110074033 Crack Stop Trenches  
Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing...
US20080093744 Anodization  
Embodiments of anodization are disclosed.
US20130026633 Multilayer Metallization with Stress-Reducing Interlayer  
A wiring structure for a semiconductor device includes a multilayer metallization having a total thickness of at least 5 μm and an interlayer disposed in the multilayer metallization with a first...
US20060022343 Very thick metal interconnection scheme in IC chips  
A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective...
US20080079159 Focused stress relief using reinforcing elements  
In a method and system for relieving stress induced within a dielectric layer of a semiconductor device (100), areas in the dielectric layer (236, 238, 242) where the stress exceeds a threshold...
US20070278681 Interconnection structure design for low RC delay and leakage  
An interconnection structure for integrated circuits having reduced RC delay and leakage is provided. The interconnection structure includes a first conductive line in a first dielectric layer, a...
US20070102819 Method for producing an integrated circuit assembly with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement  
A method is disclosed for producing an integrated circuit arrangement with an auxiliary indentation, particularly with aligning marks, and an integrated circuit arrangement. The invention also...
US20050189653 Dual damascene intermediate structure and method of fabricating same  
An intermediate structure from which a dual damascene structure may be fabricated includes a first-formed, unfaceted via hole and an intersecting trench both formed by gas plasma etching of a...
US20060017166 Robust fluorine containing Silica Glass (FSG) Film with less free fluorine  
A semiconductor device and method of manufacture thereof having a less free fluorine (F) fluorine containing Silica Glass (FSG) dielectric film formed thereon. The FSG dielectric film includes...
US20140264880 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME  
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a...
US20120018889 PROCESS FOR PRODUCING A METALLIZATION LEVEL AND A VIA LEVEL AND CORRESPONDING INTEGRATED CIRCUIT  
A process for producing an upper metallization level and a via level connecting this upper metallization level to a lower metallization level includes: producing an insulating region on the lower...
US20070226995 SYSTEM AND METHOD FOR ADHERING LARGE SEMICONDUCTOR APPLICATIONS TO PCB  
A system and method for reducing power losses in a semiconductor device, especially a photovoltaic cell. The system includes a semiconductor device that includes at least one conductive crossbar...
US20060261484 Electronic apparatus having polynorbornene foam insulation  
Various apparatus and systems include foamed polynorbornene insulating material. The foamed polynorbornene material may provide electrical insulation between conductive layers of an integrated...
US20110215475 MULTI-SURFACE IC PACKAGING STRUCTURES  
An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more...
US20060035457 Interconnection capacitance reduction  
An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the...
US20110241212 STRESS LAYER STRUCTURE  
A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and...
US20090321939 Through Silicon via Bridge Interconnect  
An integrated circuit bridge interconnect system includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The...
US20050224980 Interconnect adapted for reduced electron scattering  
A die is provided with an interconnect, and the grain structure of the interconnect is adapted to reduce electron scattering.
US20070210453 Dummy-fill-structure placement for improved device feature location and access for integrated circuit failure analysis  
An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The...
US20100038790 RELIABILITY OF WIDE INTERCONNECTS  
An integrated circuit which includes a semiconductor substrate, a first metal wiring level on the semiconductor substrate which includes metal wiring lines, an interconnect wiring level on the...
US20070052100 Spring clip for a portable electronic device  
A portable electronic device spring clip including a first retention section adapted to attach the spring clip to a framework; a second retention section adapted to be located at a top side of a...
US20060175704 Current collecting structure and electrode structure  
An object of this invention is to achieve the current collecting structure and the electrode structure with good electrical conductivity and ionic conductivity which are comprised of the current...
US20050087877 Differential signal traces coupled with high permittivity material  
In some embodiments, an apparatus includes a substrate and a pair of signal traces formed on the substrate. The signal traces may be spaced apart from each other. The apparatus may also include a...

Matches 1 - 50 out of 437 1 2 3 4 5 6 7 8 9 >