Matches 1 - 50 out of 98 1 2 >


Match Document Document Title
US20110221044 TUNGSTEN BARRIER AND SEED FOR COPPER FILLED TSV  
Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for...
US20120292771 FABRICATING A CONTACT RHODIUM STRUCTURE BY ELECTROPLATING AND ELECTROPLATING COMPOSITION  
A contact rhodium structure is fabricated by a process that comprises obtaining a substrate having a dielectric layer thereon, wherein the dielectric layer has cavities therein into which the...
US20130200520 THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING  
At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device...
US20130113106 THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING  
At least one metal adhesion layer is formed on at least a Cu surface of a first device wafer. A second device wafer having another Cu surface is positioned atop the Cu surface of the first device...
US20140246776 DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING  
A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy...
US20150255331 INTEGRATED CIRCUITS WITH A COPPER AND MANGANESE COMPONENT AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS  
Integrated circuits with copper and magnesium components and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming an aperture...
US20120098133 STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES  
The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of...
US20050029660 Adhesions of structures formed from materials of poor adhesion  
Semiconductor device having a substrate, at least one adhesion promoter core, which is deposited on a part of the substrate, and a deposit, which completely surrounds the adhesion promoter core,...
US20120013010 BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME  
A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is...
US20060258153 Barrier assembly for an exposure apparatus  
A barrier assembly (58) for sealing an assembly gap (274) between a first assembly (266) and a second assembly (268) includes a first barrier (270) that seals the assembly gap (274) and a second...
US20050067702 Plasma surface modification and passivation of organo-silicate glass films for improved hardmask adhesion and optimal RIE processing  
Interconnect structure having enhanced adhesion between the various interfaces encompassing an organo-silicate glass (OSG) film, for use in semiconductor devices is provided herein. The novel...
US20120292770 METHOD AND DEVICE FOR PREVENTING CORROSION ON SENSORS  
A device for preventing corrosion on sensors and a method of fabricating the same is disclosed, wherein the device comprises an insulation layer and an adhesion layer covering a metallization...
US20080116578 Initiation layer for reducing stress transition due to curing  
An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k...
US20130168864 METHOD FOR PRODUCING ULTRA-THIN TUNGSTEN LAYERS WITH IMPROVED STEP COVERAGE  
A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method...
US20050179137 Semiconductor device having copper damascene interconnection and fabricating method thereof  
A silicon carbon nitride film is formed on an interlayer dielectric film having Si—H bonds and a Cu interconnection. The silicon carbon nitride film has the role of blocking moisture absorption...
US20100038789 CONFORMAL ADHESION PROMOTER LINER FOR METAL INTERCONNECTS  
A dielectric layer is patterned with at least one line trough and/or at least one via cavity. A metallic nitride liner is formed on the surfaces of the patterned dielectric layer. A metal liner is...
US20110031625 Method of Processing a Contact Pad, Method of Manufacturing a Contact Pad, and Integrated Circuit Element  
An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation...
US20120205808 MEMS and Protection Structure Thereof  
A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which...
US20110031624 MEMS and a Protection Structure Thereof  
A protection structure of a pad is provided. The pad is disposed in a dielectric layer on a semiconductor substrate and the pad includes a connection region and a peripheral region which...
US20150179579 COBALT BASED INTERCONNECTS AND METHODS OF FABRICATION THEREOF  
An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a...
US20150041982 STACKED REDISTRIBUTION LAYERS ON DIE  
Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the...
US20100308463 INTERFACIAL CAPPING LAYERS FOR INTERCONNECTS  
Adhesive layers residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Adhesion...
US20050136638 Low temperature sintering nanoparticle compositions  
A composition contains a mixture of silver and gold metallic nanoparticles. The composition can be deposited on a substrate and sintered to form a conductive element.
US20090152727 BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME  
A bonding pad includes a conductive layer formed over an insulation layer, and a dummy pattern penetrating the insulation layer and stuck in the conductive layer, wherein a bonding process is...
US20130193579 STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME  
A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes...
US20050205997 Device with through-hole interconnection and method for manufacturing the same  
A device having improved electrical connection includes a first substrate including a first side and a second side; a functional element on the first side of the first substrate; a pad that is...
US20050116344 Microelectronic element having trace formed after bond layer  
An article is provided which includes a structure overlying a face of an element. The structure includes a first metal layer and a wettable metal layer overlying the first metal layer. A...
US20110049515 CHIP STRUCTURE WITH BUMPS AND TESTING PADS  
A chip structure comprising a silicon substrate, a MOS device, dielectric layers, a metallization structure, a passivation layer, a plurality of metal layers and a polymer layer. The metallization...
US20080164613 ULTRA-THIN Cu ALLOY SEED FOR INTERCONNECT APPLICATION  
A copper interconnection structure which is electroplated onto a silicon layer or semiconductor substrate. The structure includes an ultra-thin copper seed alloy incorporating selectively minor...
US20100117236 TOP LAYERS OF METAL FOR HIGH PERFORMANCE IC'S  
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post passivation. The thick,...
US20080136032 METHOD FOR FILLING A CONTACT HOLE AND INTEGRATED CIRCUIT ARRANGEMENT WITH CONTACT HOLE  
A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a...
US20080230910 INTEGRATED CIRCUIT AND METHOD FOR PRODUCING THE SAME  
An integrated circuit provides a carrier substrate, a wiring level above a carrier substrate, wherein the wiring level comprises a first conductor track composed of a first conductive material and...
US20050098890 Method for producing an adhesive bond and adhesive bond between a chip and a planar surface  
A method for producing an adhesive bond between a chip and a planar surface and the arrangement of the adhesive bond are discussed. A flexible coupling medium is applied on the planar surface or...
US20080265419 SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME  
A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A...
US20110285022 INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME  
A method for fabricating an integrated circuit (IC) chip includes forming a metal trace having a thickness of between 5 μm and 27 μm over a semiconductor substrate, and forming a passivation layer...
US20060118955 Robust copper interconnection structure and fabrication method thereof  
An interconnect structure has a silicon nitride layer overlying a substrate with a conductive region, a silicon carbide layer overlying the silicon nitride layer, and a dielectric layer having a...
US20120112348 DEVICES, METHODS, AND SYSTEMS FOR WAFER BONDING  
Devices, methods, and systems for wafer bonding are described herein. One or more embodiments include forming a bond between a first wafer and a second wafer using a first material adjacent the...
US20080237866 SEMICONDUCTOR DEVICE WITH STRENGTHENED PADS  
A semiconductor device is provided having an increased hardness against contact of a probe needle. The semiconductor device includes: a semiconductor substrate; a semiconductor element formed in...
US20150076698 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME  
The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate...
US20070040274 INTERCONNECT OF GROUP III- V SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR MAKING THE SAME  
An interconnect of the group III-V semiconductor device and the fabrication method for making the same are described. The interconnect includes a first adhesion layer, a diffusion barrier layer...
US20080237865 SEMICONDUCTOR DEVICE INCLUDING AN AMORPHOUS NITRIDED SILICON ADHESION LAYER AND METHOD OF MANUFACTURE THEREFOR  
Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a...
US20140061921 GOLD BONDING IN SEMICONDUCTOR DEVICES USING POROUS GOLD  
A method of manufacturing comprising providing a semiconductor layer having metal adhesion layer on a planar surface of the semiconductor layer and an alloy layer on the metal adhesion layer, the...
US20070257261 METHOD FOR FORMING METAL WIRING, METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE, DEVICE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPRATUS  
A device includes a substrate; a bank provided on the substrate; and a metal wiring in a wiring forming region of the substrate that is sectioned by the bank with a liquid phase method. The metal...
US20070262449 Coating method and solutions for enhanced electromigration resistance  
The present invention concerns a methods and compositions for preparing a multi layer composite device, such as a semiconductor device. Said method comprises (A) forming a dielectric layer on the...
US20070296082 Semiconductor device having conductive adhesive layer and method of fabricating the same  
In a semiconductor device, a semiconductor substrate may include a plurality of first conductive pads. An insulating isolation layer may be on the semiconductor substrate so as to separate the...
US20150221612 THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS  
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal...
US20120161282 Method for Forming a Ruthenium Film  
Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.
US20080012136 Metal Interconnection Structure of Semiconductor Device and Method for Manufacturing the Same  
Disclosed are a metal interconnection structure of a semiconductor device and a method for manufacturing the same. The structure includes an upper interlayer dielectric layer pattern including...
US20120161323 SUBSTRATE FOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME  
Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a...
US20090026619 Method for Backside Metallization for Semiconductor Substrate  
A wafer circuit, such as a wafer-level package, that includes a semiconductor substrate on which is fabricated one or more integrated circuits. A backside metal layer is deposited on the...

Matches 1 - 50 out of 98 1 2 >