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US20170186694 DEVICES AND METHODS RELATED TO A SPUTTERED TITANIUM TUNGSTEN LAYER FORMED OVER A COPPER INTERCONNECT STACK STRUCTURE  
Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including an ohmic...
US20130285245 MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES  
A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the...
US20100007023 MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE HAVING IMPROVED COPPER DIFFUSION PREVENTIVE FUNCTION OF PLUGS AND WIRINGS MADE OF COPPER OR COPPER ALLOY  
(a) A copper alloy film containing at least two types of metal elements in addition to copper is formed on the surface of an insulator containing oxygen and formed on a semiconductor substrate....
US20090243106 STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION  
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary...
US20140061919 Electroplated Metallic Interconnects And Products  
One embodiment of the present invention is a device including at least a portion of a void-free electroplated metallic interconnect embedded in an opening, said opening having sidewalls, said...
US20110140276 INTERLAYER INSULATING FILM, INTERCONNECTION STRUCTURE, AND METHODS OF MANUFACTURING THE SAME  
This invention provides an interlayer insulating film for a semiconductor device, which has low permittivity, is free from the evolution of gas such as CFx and SiF4 and is stable, and a wiring...
US20080290516 SEMICONDUCTOR DEVICE WITH BONDING PAD SUPPORT STRUCTURE  
A semiconductor device having bonding pads on a semiconductor substrate includes: an upper copper layer that is formed on the lower surface of the bonding pads with a barrier metal interposed and...
US20060237846 DOPED NITRIDE FILM, DOPED OXIDE FILM AND OTHER DOPED FILMS AND DEPOSITION RATE IMPROVEMENT FOR RTCVD PROCESSES  
When forming a silicon nitride film from a nitrogen precursor, using a silicon precursor combination rather than a single silane precursor advantageously increases the deposition rate. For...
US20110309510 ARRAY SUBSTRATE, DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME  
An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal...
US20080099920 MULTI-STAGE CURING OF LOW K NANO-POROUS FILMS  
Embodiments in accordance with the present invention relate to multi-stage curing processes for chemical vapor deposited low K materials. In certain embodiments, a combination of electron beam...
US20070035025 Damascene processing using dielectric barrier films  
Damascene processing is implemented with dielectric barrier films for improved step coverage and reduced contact resistance. Embodiments include the use of two different dielectric films to avoid...
US20060138660 Copper interconnect  
An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a...
US20060071336 Copper interconnect  
An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device....
US20060001161 Electrical contact for high dielectric constant capacitors and method for fabricating the same  
An electrical contact includes a non-conductive spacer surrounding conductive plug material along the full height of the contact. The spacer inhibits oxide and other diffusion through the contact....
US20150084196 Devices Formed With Dual Damascene Process  
Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench...
US20140159241 Structures and Methods to Enhance Copper Metallization  
Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary...
US20070045856 Mixed metal nitride and boride barrier layers  
Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw...
US20080136030 Semiconductor device comprising a doped metal comprising main electrode  
A semiconductor device is provided comprising a main electrode (4) and a dielectric (3) in contact with the main electrode (4), the main electrode (4) comprising a material having a work function...
US20160197038 SELF-ALIGNED VIA INTERCONNECT STRUCTURES  
A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes...
US20130207267 INTERCONNECTION STRUCTURES IN A SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME  
Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a...
US20130127057 SEED LAYER PASSIVATION  
A microfeature workpiece generally includes a first conducting layer, a chemisorbed layer or a monolayer directly on the first conducting layer, and a second conducting layer. The chemisorbed...
US20100187694 Through-Silicon Via Sidewall Isolation Structure  
A system and method for an improved through-silicon via isolation structure is provided. An embodiment comprises a semiconductor device having a substrate with electrical circuitry formed thereon....
US20140197537 Void-Free Metallic Filled High Aspect Ratio Openings  
One embodiment is a device which includes at least one filled via or trench wherein the at least one filled via or trench includes void-free filled metal or alloy, and the filled via or trench has...
US20100200991 Dopant Enhanced Interconnect  
Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin...
US20140117551 PROCESSING SYSTEM FOR FORMING FILM ON TARGET OBJECT  
A processing system for forming a film on a target object having thereon an insulating layer that is made of a low-k film and having a recess is provided. The processing system comprises: a...
US20130214416 INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES  
Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer....
US20090321938 Methods of Manufacturing Copper Interconnect Systems  
An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner...
US20070194450 BEOL compatible FET structure  
This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication...
US20060038293 Inter-metal dielectric fill  
An inter-metal dielectric (IMD) fill process includes depositing an insulating nanolaminate barrier layer. The nanolaminate is preferably an oxide liner formed by using an alternating layer...
US20170047248 FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES  
A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate...
US20160307796 SELF-FORMING, SELF-ALIGNED BARRIERS FOR BACK-END INTERCONNECTS AND METHODS OF MAKING SAME  
Processes of forming an insulated wire into an interlayer dielectric layer (ILD) of a back-end metallization includes thermally treating a metallic barrier precursor under conditions to cause at...
US20150001720 Interconnect Structure and Method for Forming Interconnect Structure  
An improved interconnect structure and a method for forming the interconnect structure is disclosed that allows the interconnect structure to achieve a lower Rc. To lower the Rc of the...
US20100224996 METHODS OF MANUFACTURING COPPER INTERCONNECT SYSTEMS  
An integrated circuit (IC) may include a substrate, a first dielectric layer adjacent the substrate, and at least one trench in the first dielectric layer. The IC may also include a metal liner...
US20080012134 METAL INTERCONNECTION STRUCTURES AND METHODS OF FORMING THE SAME  
A method of forming a metal interconnection structure is provided. The method includes forming an insulating layer on a semiconductor substrate including a first metal interconnection. The...
US20150371925 THROUGH ARRAY ROUTING FOR NON-VOLATILE MEMORY  
Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a...
US20130140700 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE  
Provided is a method of manufacturing a TSV structure, which prevents a substrate from warping even if it is made thin. A method of manufacturing a semiconductor device comprises integrating...
US20130037954 Metallization and Its Use In, In Particular, an IGBT or a Diode  
A vertical power semiconductor component includes a semiconductor chip and at least one layer serving as a heat sink. The semiconductor chip has a top main surface at a front side of the...
US20090302474 Atomic laminates for diffucion barrier applications  
The present invention relates to a very thin multilayer diffusion barrier for a semiconductor device and fabrication method thereof. The multilayer diffusion barrier according to the present...
US20090140430 Copper Alloy Sputtering Target and Semiconductor Element Wiring  
A first copper alloy sputtering target comprising 0.5 to 4.0 wt % of Al and 0.5 wtppm or less of Si and a second copper alloy sputtering target comprising 0.5 to 4.0 wt % of Sn and 0.5 wtppm or...
US20090026618 Semiconductor device including interlayer interconnecting structures and methods of forming the same  
In a method of forming a semiconductor device, and a semiconductor device formed according to the method, an insulating layer is provided on an underlying contact region of the semiconductor...
US20160056106 STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME  
A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The...
US20100207274 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD  
A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a...
US20100078820 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME  
A metal barrier film which contains an additive element is formed on the side face and on the bottom of a trench formed in an insulating film; a seed film is formed over the metal barrier film; a...
US20080185722 Formation process of interconnect structures with air-gaps and sidewall spacers  
An integrated circuit structure having air gaps is provided. The integrated circuit includes a conductive line; a sidewall spacer on a sidewall of the conductive line, wherein the sidewall spacer...
US20050263891 Diffusion barrier for damascene structures  
A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying...
US20050205997 Device with through-hole interconnection and method for manufacturing the same  
A device having improved electrical connection includes a first substrate including a first side and a second side; a functional element on the first side of the first substrate; a pad that is...
US20160133577 Wiring Structures and Methods of Forming the Same  
A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a...
US20150357236 Ultrathin Multilayer Metal Alloy Liner for Nano Cu Interconnects  
Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic...
US20150123278 SEMICONDUCTOR DEVICES, METHODS OF MANUFACTURING THE SAME, MEMORY CARDS INCLUDING THE SAME AND ELECTRONIC SYSTEMS INCLUDING THE SAME  
Semiconductor devices are provided. The semiconductor device includes a through electrode penetrating a substrate such that an end portion of the through electrode protrudes from a surface of the...
US20100320607 INTERCONNECT STRUCTURES WITH A METAL NITRIDE DIFFUSION BARRIER CONTAINING RUTHENIUM  
A method for forming an interconnect structure for copper metallization and an interconnect structure containing a metal nitride diffusion barrier are described. The method includes providing a...

Matches 1 - 50 out of 411 1 2 3 4 5 6 7 8 9 >