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US20140035135 SOLDER BUMP FOR BALL GRID ARRAY  
A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width...
US20130207261 MAINTAINING ALIGNMENT IN A MULTI-CHIP MODULE USING A COMPRESSIBLE STRUCTURE  
An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative...
US20150130061 Bump-on-Trace Methods and Structures in Packaging  
A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder...
US20110012261 Post bump and method of forming the same  
A post bump formed over an electrode pad of a substrate for electrically connecting to an external device, the post bump including a metal post formed over the electrode pad; and a solder formed...
US20130270699 Conical-Shaped or Tier-Shaped Pillar Connections  
A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar...
US20140015133 SUPPLY VOLTAGE OR GROUND CONNECTIONS FOR INTEGRATED CIRCUIT DEVICE  
Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together...
US20140328596 COMBINATION UNDERFILL-DAM AND ELECTRICAL-INTERCONNECT STRUCTURE FOR AN OPTO-ELECTRONIC ENGINE  
A combination underfill-dam and electrical-interconnect structure for an opto-electronic engine. The structure includes a first plurality of electrical-interconnect solder bodies. The first...
US20110156253 MICRO-BUMP STRUCTURE  
A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the...
US20120326308 ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS  
A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.
US20110227219 ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS  
A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.
US20120146219 WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS  
An interconnect structure comprises a solder including nickel (Ni) in a range of 0.01 to 0.20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer...
US20120104605 Chip Design having Integrated Fuse and Method for the Production Thereof  
A chip design (1) comprising an external supply connection (VBAT), an internal supply connection (VDD), an integrated circuit (2) that is coupled to the internal supply connection (VDD) for...
US20140291843 HYBRID SOLDER AND FILLED PASTE IN MICROELECTRONIC PACKAGING  
Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used...
US20110101527 MECHANISMS FOR FORMING COPPER PILLAR BUMPS  
The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The...
US20150179592 SELF-ALIGNED UNDER BUMP METAL  
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the...
US20110291275 METHOD OF ASSEMBLING CHIPS  
A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the...
US20150108642 STRUCTURE TO PREVENT SOLDER EXTRUSION  
A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond...
US20130001778 BUMP-ON-TRACE (BOT) STRUCTURES  
A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The...
US20150035147 Fine Pitch stud POP Structure and Method  
A fine pitch stud POP structure and method is disclosed. The studs are made in bonding pads on the top surface of a lower substrate, which greatly increase the height of the interconnection such...
US20110018131 BONDING PAD FOR PREVENTING PAD PEELING  
A bonding pad includes multiple metal layers, insulation layers disposed between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer and an underlying metal layer...
US20120168948 COPPER PILLAR FULL METAL VIA ELECTRICAL CIRCUIT STRUCTURE  
An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry...
US20110204515 IC DIE INCLUDING RDL CAPTURE PADS WITH NOTCH HAVING BONDING CONNECTORS OR ITS UBM PAD OVER THE NOTCH  
An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second...
US20130313705 IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK  
A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled...
US20120032330 MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS  
Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin...
US20090302446 SEMICONDUCTOR PACKAGE FABRICATED BY CUTTING AND MOLDING IN SMALL WINDOWS  
A method for cutting and molding in small windows of a window-type semiconductor package and the semiconductor package fabricated from the same are revealed. According to the method, a substrate...
US20050275096 Pre-doped reflow interconnections for copper pads  
A metal interconnect structure (100) comprising a bond pad (110) of copper; a body (103) of eutectic alloy in contact with the bond pad, this alloy including copper; and a contact pad (120)...
US20120269489 DRAM PACKAGE, DRAM MODULE INCLUDING DRAM PACKAGE, GRAPHIC MODULE INCLUDING DRAM PACKAGE AND MULTIMEDIA DEVICE INCLUDING DRAM PACKAGE  
A DRAM package includes a DRAM package body, and a ball grid array formed at a lower surface of the DRAM package body. The ball grid array includes a plurality of solder balls arranged in the...
US20150115442 Redistribution layer and method of forming a redistribution layer  
A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at...
US20140252608 Method and Apparatus for Packaging Pad Structure  
Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top...
US20120235297 WAFER LEVEL PACKAGING OF MEMS DEVICES  
A MEMS device is disclosed. The MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being...
US20080197493 Integrated circuit including conductive bumps  
One embodiment provides an integrated circuit including an electrical contact and a conductive bump elongated via centrifugal forces. The conductive bump has a base and a top. The base is attached...
US20150252217 UNDERFILL COMPOSITION FOR ENCAPSULATING A BOND LINE  
An underfill composition for encapsulating a bond line and a method of using the underfill composition are described. Advantageously, the disclosed underfill composition in an uncured state has a...
US20110291273 CHIP BUMP STRUCTURE AND METHOD FOR FORMING THE SAME  
A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening...
US20130026630 FLIP CHIPS HAVING MULTIPLE SOLDER BUMP GEOMETRIES  
In certain embodiments, a flip chip includes a first and second solder bump. The first solder bump has a solder bump height that is greater than the second solder bump. In certain embodiments, a...
US20130285239 CHIP ASSEMBLY AND CHIP ASSEMBLING METHOD  
A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a...
US20100032835 COMBINATION VIA AND PAD STRUCTURE FOR IMPROVED SOLDER BUMP ELECTROMIGRATION CHARACTERISTICS  
The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A...
US20100059883 METHOD OF FORMING BALL BOND  
A method of forming a ball bond (10) includes forming a bonding ball (12) at an end of a bonding wire (16). The bonding ball (12) is preformed to a substantially ball bond shape at a preform...
US20110057313 Enhanced Copper Posts for Wafer Level Chip Scale Packaging  
An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered...
US20120104604 CRACK ARREST VIAS FOR IC DEVICES  
An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of...
US20110215472 Through Silicon via Bridge Interconnect  
An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The...
US20090108447 SEMICONDUCTOR DEVICE HAVING A FINE PITCH BONDPAD  
A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to...
US20110140271 INTEGRATED CIRCUIT CHIP WITH PYRAMID OR CONE-SHAPED CONDUCTIVE PADS FOR FLEXIBLE C4 CONNECTIONS AND A METHOD OF FORMING THE INTEGRATED CIRCUIT CHIP  
Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a...
US20110254001 HIGH PERFORMANCE SUB-SYSTEM DESIGN AND ASSEMBLY  
A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The...
US20140084461 FLUX MATERIALS FOR HEATED SOLDER PLACEMENT AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS  
Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing...
US20130075904 COPLANER WAVEGUIDE TRANSITION  
A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar...
US20140138823 VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING  
One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first...
US20140264854 MULTI-CHIP MODULE WITH SELF-POPULATING POSITIVE FEATURES  
A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates....
US20090091032 Bond Pad Design for Fine Pitch Wire Bonding  
A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such...
US20100295189 METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS  
A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block...
US20080251916 UBM structure for strengthening solder bumps  
A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically...